Abstract: A single ended input differential output amplifier (100) and integrated circuit including such an amplifier (100). A pair of load resistors (102, 104) are connected between a supply voltage (Vdd) and differential outputs OUTP and OUTM. An inductor (106) is connected between input RFIN and a source bias voltage VBS. A first field effect transistor (FET) (108) is connected, drain to source, between load resistor (102) at output OUTP and inductor (106) at RFIN. A second FET (110) is connected, drain to source, between the second load resistor (104) at output OUTM and the source bias voltage VBS. A gate bias voltage VBg is connected to the gate of FET (108) and through resistor (112) to the gate of FET (110). A coupling capacitor (114) is connected between the input RFIN and the gate of FET (110).

Abstract: Solder paste (16) is dispensed onto a platen (12) that includes depressions (14) that are preferably conical or in an inverted pyramid shape. The solder paste (16) is formed of a plurality of particles composed of a solder alloy. Excess solder paste (16) is removed, and a predetermined solder paste volume fills the depressions (14). A substrate (18) is superposed onto platen (12) such that solder-wettable bond pads (20) on the substrate (18) register with the depressions (14). The platen (12) is heated to melt the solder alloy, and the solder alloy coalesces to form molten solder droplets (22). The solder droplets (22) are transferred onto the solder-wettable bond pads (20) to form solder bumps (24) bonded to the bond pads (20).

Abstract: Binding of a molecule to a molecular receptor is sensed using a transistor having a gate located at a binding site. The channel conductance of the transistor is modified by a charge associated with the molecule when the molecule binds with the molecular receptor. A modified electrical characteristic of the transistor which results is sensed to sense the binding event. Electric field enhancement is provided by applying a voltage to the gate. A second sensing transistor can be coupled to the sensing transistor to form a differential pair. The differential pair allows for enhancing and sensing of differential binding events.

Abstract: An integrated circuit microprocessor has on-board programmable chip select logic. Each of several chip select outputs is individually programmable by means of one or more control register bit fields. For instance, each chip select is asserted for bus cycles within an address range whose starting address and block size are both programmable. In addition, each chip select can be programmed to be active on read cycles only, on write cycles only, or on both read and write cycles. Each chip select can be programmed to be active during interrupt acknowledge cycles only if the interrupt being acknowledged has the same priority level as has been programmed for that chip select. In addition, the timing of the assertion of each chip select is programmable to coincide with either the address strobe or data strobe of the bus cycle. The chip select logic is designed so that it is configured to come out of reset by producing an active chip select signal during the first bus cycle run by the processor following the reset.

Abstract: A data processor has a microcode memory which is reduced in size by sharing word locations having the same contents. When one of the shared word locations is addressed, a control signal is generated and coupled to a select circuit. The select circuit outputs a predetermined operand in place of the contents of the addressed shared word location which can contain a "do not care" operand value. Selective sharing or combining of the word locations is utilized when structuring the memory to optimize savings in circuit area.

Abstract: A digital computing system having a low power mode of operation includes a mechanism for communicating, prior to entering the low power mode, information determinative of which events shall be capable of causing the termination of the low power mode. An integrated circuit microcomputer enters a low power mode in response to executing an LPSTOP instruction. Only reset events and those interrupt events having a priority level sufficiently high to pass an interrupt mask are capable of causing the termination of the low power mode. The LPSTOP instruction causes immediate data to be loaded into a status register, resetting the interrupt mask bits. The interrupt mask is then written, by means of a special bus cycle, into an interrupt mask register in a sub-system within the microcomputer. This subsystem then shuts down the clock signals to the remainder of the microcomputer, leaving only this sub-system active.

Abstract: A data processing apparatus having a bus speed counter for determining the bus speed of a previous bus cycle. This previous bus speed information is then used to optimize bus utilization. This bus speed information is particularly useful for determining whether to run prefetch bus cycles during the execution of a conditional branch instruction. If previous bus cycles have been slow, prefetch procrastination can occurs until the branch condition resolves.

Abstract: A digital timer apparatus incorporates a free running counter, an interval timer, a capture register, a pulse accumulator; holding logic and mode selection logic. In one mode of operation, a rising or falling edge of an external signal causes the current contents of the free running counter to be loaded into the capture register, causes the previous value of the capture register to be transferred to a holding register and causes the pulse accumulator to be incremented. A read of the capture holding register causes the pulse accumulator value to be transferred to a holding register and causes the pulse accumulator to be reset. The output of the interval timer can cause an interrupt signal to be generated to request service from a central processing unit.

Abstract: A register having a selective wait feature includes logic for receiving a new value to be stored and logic for selectively delaying the appearance of the new value at the output of the register until some predetermined event has occurred. The register can also be read to determine whether the event has occurred. The register is disclosed in the context of a microprocessor-controlled digital timer apparatus which responds to an incoming pulse train. Certain control bits in the apparatus determine whether the digital timer is responsive to rising edges of the pulse train, falling edges, any edges, or no edges. The microprocessor determines, at the time new values are stored to those control bit locations, whether the new values are to become effective immediately or are to be delayed until some intervening event has occurred. The register permits control over the time at which transitions between different operating modes are made in order to assure orderly operation.

Abstract: A data processor has at least one output terminal which a user of the data processor can vary the output impedance thereof depending upon the application environment of the data processor. A first output buffer of an output buffer stage has a predetermined output impedance and is coupled between an input of the stage and the output terminal. The first output buffer provides a first output terminal impedance. A second output buffer having a lower output impedance than the first output buffer may be selectively coupled in parallel to the first output buffer to reduce the output impedance of the output terminal. The coupling of the output buffers is controlled by a user of the data processor who provides a control input for selecting one of a plurality of predetermined output terminal impedance values.

Abstract: An analog-to-digital conversion system and method provide selectable data formats for each converted digital result value. Each digital result is stored in a register or table word. Information from a host processor is used to select a desired data format. In one embodiment the address range used to read the digital result serves to select the appropriate data format option, which may be, for example, left-justified or right-justified data, and signed or unsigned data. In another embodiment, one or more command words from the processor are used to select the desired data format.

Abstract: An interrupt test circuit is provided on the same chip with a microprocessor system having a central processing unit, and an interrupt controller controlling execution of an interrupt operation of the central processing unit in response to an interrupt request signal from peripheral units. The interrupt test circuit is connected between the peripheral units and the interrupt controller and includes a test signal output connected to the interrupt controller, and storage means for storing an interrupt request test signal when receiving a predetermined signal and for supplying the test signal through the test signal output to the interrupt controller for interrupt performance test.

Abstract: Data processing units (14) within an integrated circuit (10) are connected by a common bus (16). Each data processing unit follows a predetermined protocol for communicating to other data processing units via the common bus (16). Further, predetermined control and/or data processing signals within the common bus (16) are multi-tasked (i.e. function multiplexed) for a normal and special modes of operation. A state machine (21) within each data processing unit (12) controls a clock circuit (23). The state machine (21) has a predetermined state diagram for controlling clock signals associated with the predetermined modes of operation.

Abstract: A data processor having a microsequencer which reduces power consumption selectively activates instruction decode units and a microcode sequence control memory unit. The microsequencer has an instruction decode unit implemented with a plurality of PLAs and also has a microcoded ROM for providing the next microaddress. The instruction decode unit outputs a next microaddress, a next-PLA field, and a ROM-or-PLA control bit. The control bit functions to minimize power in the data processor. The next-PLA field is latched and used to select a single decode unit when the next instruction decode is needed to activate a predetermined decode unit. Early macroinstruction branching can be performed in the data processor thereby improving performance.

Abstract: A data processor with memory within a single integrated circuit package provides a programmable "secure mode" of operation to selectively restrict access and protect information stored in its memory. The secure mode of operation is included in addition to a "single chip mode" wherein the data processor accesses both data and instructions strictly from within the single integrated circuit package. An "expanded mode" of operation also exists wherein the data processor may access either internal or external memory for both instructions and data. The secure mode of operation restricts accesses of instructions to memory contained within the single integrated circuit while allowing data accesses to memory either internal or external to the integrated circuit. The secure mode is accomplished by selectively isolating internal data/instruction bus transfer activity from an external data/instruction bus.

Abstract: A digital data processor is capable of performing limited modulo arithmetic. The base, M, of the modulo arithmetic to be preformed by the processor must be equal to 2.sup.X, where X is an integer. The method and apparatus is particularly useful for generating addresses for a circular buffer or queue data structure and avoids both the large amount of hardware required for general modulo arithmetic and the software overhead associated with the use of linear arithmetic to generate modulo addresses. According to this method, X is represented as a first digital value. This representation of X is ANDed with a second digital data value (an offset). The result is then ADDed linearly with a third digital data value (a current address with the buffer). During this addition process, certain carry-out signals are inhibited from propagating, according to the digital representation of X.

Abstract: A data processor having a microsequencer which reduces power consumption selectively activates instruction decode units and a microcode sequence control memory unit. The microsequencer has an instruction decode unit implemented with a plurality of PLAs and also has a microcoded ROM for providing the next microaddress. The instruction decode unit outputs a next microaddress, a next-PLA field, and a ROM-or-PLA control bit. The control bit functions to minimize power in the data processor. The next-PLA field is latched and used to select a single decode unit when the next instruction decode is needed to activate a predetermined decode unit. Early macroinstruction branching can be performed in the data processor thereby improving performance.