Abstract: A user through a personal computer, in real time, controls the activation and selection of voice and data transmission paths in a communication network independent of network profiles. The network includes a public switched telephone network and a data network, e.g. the Internet for voice and/or data transmissions over either the voice or data networks. In the network, a voice terminal and a computer terminal are coupled to a shared voice and data terminal. A digital subscriber line access multiplexer is coupled to the shared voice and data terminal; the data network through a client server interface, and a voice network through an intelligent switch. The client server interface includes programmable stored data descriptive of network-authorized data and voice functions and transmission paths in the voice and data networks. The interface is linked to the multiplexer and switch for transmitting signaling messages directing traffic to the voice and data networks in accordance with the stored data.

Abstract: A secure server in a secure distributed information system isolates interaction from terminals to specific personal vaults including and to only those personal vaults, creating a "virtual logon". The secure server includes a secure connection server coupled to the system and to a vault deposit server having personal vaults in which user specific vault processes execute on dedicated encrypted data, after authentication of the user by a vault supervisor. The supervisor forwards vault process results to the user through the browser.

Abstract: A domino logic simulator for a CMOS domino logic circuit seeds all logic circuits under test with an "X" state before initialization of a special simulator machine cycle devoted to validating all pre-charge circuits in each stage of the CMOS domino logic circuit. In the special machine cycle, each stage of the circuit receives a discrete clock signal which is applied to the pre-charge and logic devices in precharge and evaluation phase sequences. The clock phase sequences in each stage propagate the "X" state at each logic circuit through the succeeding stages to provide an "X" output for the machine cycle, except a "0" state is provided as an output at the end of the machine cycle if the precharge circuit in each stage is functioning properly during the precharge sequences of the clock cycle applied to the stage. A clocked delay reset circuit in each stage provides the output of the stage. A static logic device in each stage saves power in transferring the output of a stage to a succeeding stage.

Abstract: A Content Addressable Memory (CAM) includes a plurality of conventional CAM cells arranged in rows and columns, the CAM cells being coupled together by word lines and bit lines for reading from and writing information into the CAM cells. Each CAM cell in a row is connected to a match line which provides an indication when an input word on the bit lines matches the contents of the cells coupled to the match line. A combinatorial logic circuit including a parity generator is coupled to the word lines and provides an indication when multiple words have been selected by an input word. The combinatorial logic circuit includes an OR circuit providing a first input to an AND circuit and a parity generator providing a second input to the AND which only provides an output when multiple word lines have been selected by an input word.