Abstract: A method and apparatus for improving packet processing employing a network flow control mechanism are disclosed. A network process, in one embodiment, suspends distribution of incoming packet(s) to one or more, packet processing engines (“PEs”) upon detecting a stalling request. After identifying currently executing operations initiated by one or more kicking circuits before the issuance of stalling request, the process allows the currently executing operations to complete despite the activation of the stalling request.

Abstract: A system for general purpose input-output (IO), including a first pad; an IO buffer comprising the first pad; and an IO datapath logic block operatively connected to the IO buffer, where the IO datapath logic block and the IO buffer are associated with a general purpose IO block in a heterogeneous configurable integrated circuit (HCIC).

Abstract: A system for parsing frames including a first cell extraction circuit (CEC) configured to identify a first cell from a first frame, a first parser engine operatively connected to the first CEC, where the first parser engine is configured to generate a result based on the first cell, and a first forwarding circuit operatively connected to the first parser engine and configured to forward the result, where the first CEC, the first parser engine, and the first forwarding circuit are associated with a first frame parser unit.

Abstract: In one embodiment, the systems and methods utilizes an enciphered permit identification number, called a session certificate, to reference the policy attribute values and session key that are stored in a secured, online reference monitor (SRM). The session key is used to encipher confidential communications, such as voice and audio communications over the Internet (VoIP), between computers. Each computer uses a unique key with a cryptographic transaction protocol for authentication and key agreement (PAKE) to securely communicate with the SRM. A sender computer uses PAKE to get a session certificate and a session key from the SRM. It sends the session certificate to a receiver computer. The receiver computer sends the session certificate to the SRM and gets back the session key. The sender computer encrypts its VoIP message with the session key and transmits it to the receiver computer. The receiver computer decrypts the VoIP message.

Abstract: A method of enhancing picture quality of a video signal is disclosed. The method comprises the steps of generating a interpolated base frame image; receiving a first previously decoded difference picture; receiving a second previously decoded difference picture; generating a combined motion compensated difference surface; and generating a temporally interpolated enhanced picture based upon the interpolated base frame image and the combined motion compensated difference surface. A circuit for enhancing picture quality of a video signal is also disclosed. The circuit comprising a base decoder generating a base image of a standard definition picture; a temporal predictive interpolator coupled to the base decoder and generating an interpolated block; and a summing circuit coupled to the temporal predictive interpolated. The summing circuit preferably adds the interpolated block and a difference block.

Abstract: An apparatus and method of a network system between a host and a group of routers using virtual router redundancy protocol (“VRRP”) messages and bidirectional forwarding detection (“BFD”) sessions are disclosed. The network system is capable of facilitating a first communication between a host and a master router of multiple VRRP routers and establishing a BFD session between the host and the master router. When the BFD session fails, the priority of the master router is subsequently lowered and a backup router is activated. In one embodiment, the backup router capable of performing functions of the master router becomes a new master until the BFD session resumes.

Abstract: A method and apparatus of providing a programmable system using non-volatile programmable transistors are disclosed. A programmable logic circuit, in one embodiment, includes a first programmable transistor and a second programmable transistor. The first programmable transistor includes a first gate terminal, a first source terminal, a first drain terminal, and a first programming terminal. The second programmable transistor includes a second gate terminal, a second source terminal, and a second drain terminal, and a second programmable terminal. The first and second programmable transistors include non-volatile memory elements. The first and the second gate terminals are coupled to an input terminal, and the first drain terminal and the second source terminal are coupled to an output terminal to perform a logic function.

Abstract: A translation on demand (“TOD”), in one embodiment, receives a search request with a search term from a user in a native language across the Internet. The search term is translated into at least one foreign language using automatic translation software (“ATS”) according to specifications listed with the search request. After the search term is translated, a search with the search term in both native and foreign languages is performed. Once receipt of the outcome of the search, search results are displayed, wherein each entry or document of the search results also includes a brief description presented in the native language. The TOD system also generates multiple TOD price selections. The TOD price selections allow a user to place an order to translate a selected document. A translation job order for translating the selected document is then distributed for bidding over the network.

Abstract: A light-emitting device capable of being powered by an AC power supply or an unregulated DC power supply is disclosed. The light-emitting device, in an aspect, is coupled to a controller, a light-emitting diode (“LED”) array, and a power supply, wherein the power supply can be an AC power source or an unregulated DC power source. While the power supply provides electrical power, the controller generates various LED control signals in response to power fluctuation of the electrical power. The LED array allows at least a portion of LEDs to be activated in accordance with the logic states of the LED control signals.

Abstract: The present invention provides integrated circuits with improved logic cells. In one embodiment, an integrated circuit having a plurality of logic cells (LC) is provided, each LC comprising: a lookup table having a LUT output terminal; and, a first multiplexer; wherein, a first multiplexer input terminal is connected to of a first input terminal of the LC, a second multiplexer input terminal is connected to the LUT output terminal, a multiplexer output terminal is connected to a first output terminal of the LC, and a multiplexer select terminal is connected to a second input terminal of the LC so as to select which of the signals appearing at the first and second multiplexer input terminal to pass through; wherein, by coupling in chain the first input terminal of one LC to the first output terminal of another LC, a WLUT chain is formed.

Abstract: The present invention provides integrated circuits with improved logic cells. In one embodiment, an integrated circuit having a plurality of logic cells (LC) is provided, each LC comprising: a lookup table having a LUT output terminal; and, a first multiplexer; wherein, a first multiplexer input terminal is connected to of a first input terminal of the LC, a second multiplexer input terminal is connected to the LUT output terminal, a multiplexer output terminal is connected to a first output terminal of the LC, and a multiplexer select terminal is connected to a second input terminal of the LC so as to select which of the signals appearing at the first and second multiplexer input terminal to pass through; wherein, by coupling in chain the first input terminal of one LC to the first output terminal of another LC, a WLUT chain is formed.

Abstract: A system for determining memory addresses including a first content-addressable memory (CAM) configured to generate a first matchvector based on a first key; a first inverse-mask-reverse (IMR) module operatively connected to the first CAM, where the first IMR module is configured to generate a first auxiliary matchvector based on the first matchvector; and a first priority encoder (PE) operatively connected to the first IMR module, where the first PE is configured to output a first encoded memory address based on the first auxiliary matchvector, where the first CAM, the first IMR module, and the first PE are associated with a first reconfigurable content-addressable memory (RCAM).

Abstract: An optical device capable of generating warm light using an array of phosphor islands situated over a phosphor layer is disclosed. The device includes a solid state light emitter, a phosphor layer, and phosphor islands. The solid state light emitter, in an aspect, is a light emitting diode (“LED”) capable of converting electrical energy to optical light. The phosphor layer is disposed over the solid state light emitter for generating luminous cool light in response to the optical light. Multiple phosphor islands are disposed on the phosphor layer for converting cool light to warm light, wherein the phosphor islands are evenly distributed over the phosphor layer.

Abstract: An apparatus and method for using a direct memory access (“DMA”) to facilitate netflow statistics are disclosed. A network device such as a router or a switch, in one embodiment, includes a statistic component, a local memory, and a memory access controller. The statistic component is configured to gather information relating to net usage from packet flows or netflows in response to corresponding index values or tags. While the local memory such as a cache provides the index values or tags assignable to packet flows, the memory access controller such as a DMA transfers at least a portion of the index values or tags between the local memory and a main memory for enhancing capacity of the local memory.

Abstract: An apparatus and method for routing data packets between a routed network and a local bridged network using integrated routing and bridging (“IRB”) functions are disclosed. In one embodiment a bridge interface between a host in the local bridge network and a bridging engine is IRB enabled. An unnumbered Internet Protocol (“IP”) interface is then added between the host and a routing engine in accordance with the IRB enabled bridge interface. Subsequently packets received from the routed network are forwarded directly by the routing engine to the host in the local bridge network via the unnumbered IP interface, thereby bypassing the bridging engine. Through use of an embodiment of the present invention, packet processing delay in each network device is reduced (because of bypassing the bridging engine), thereby decreasing packet latency in an ever growing network.

Abstract: An optical device deploring a phosphor layer having a textured surface to improve output of visual light is disclosed. A light emitting device includes a solid state light emitter and a phosphor layer. The solid state light emitter, for example, is configured to convert electrical energy to optical light. The phosphor layer includes a first surface and a second surface, wherein the first surface, for example, is the top surface while the second surface is the bottom surface. The phosphor layer is disposed over the solid state light emitter for generating luminous light in response to the optical light. The first surface of the phosphor layer, in one embodiment, is configured to include a texture, which has similarly shaped uniform configurations, capable of reducing total internal reflection.

Abstract: A method and apparatus of providing a programmable system using non-volatile programmable transistors are disclosed. A programmable logic circuit, in one embodiment, includes a first programmable transistor and a second programmable transistor. The first programmable transistor includes a first gate terminal, a first source terminal, a first drain terminal, and a first programming terminal. The second programmable transistor includes a second gate terminal, a second source terminal, and a second drain terminal, and a second programmable terminal. The first and second programmable transistors include non-volatile memory elements. The first and the second gate terminals are coupled to an input terminal, and the first drain terminal and the second source terminal are coupled to an output terminal to perform a logic function.

Abstract: An apparatus and a method for enhancing digital processing implementation using non-power-of-two even count Gray coding are disclosed. The even count encoding device includes a first circuit, a second circuit, and a coding circuit. The first circuit, in one embodiment, is configured to identify a first portion of entries in a table in response to an input number. The second circuit is capable of determining a second portion of entries in the table in response to the input number, wherein the number of the first portion of entries and the number of the second portion of the entries are substantially the same. The coding circuit is operable to concatenate the second portion of the entries to the first portion of the entries to form an output table, which includes a sequence of even count integers wherein the difference between two adjacent integers is one bit position.

Abstract: A system for parsing frames including a first cell extraction circuit (CEC) configured to identify a first cell from a first frame, a first parser engine operatively connected to the first CEC, where the first parser engine is configured to generate a result based on the first cell, and a first forwarding circuit operatively connected to the first parser engine and configured to forward the result, where the first CEC, the first parser engine, and the first forwarding circuit are associated with a first frame parser unit.