Abstract: An asymmetric response latch providing immunity to single event upset without loss of speed. The latch has cross-coupled inverters having a hardened logic state and a soft state, wherein the logic state of the first inverter can only be changed when the voltage on the coupling node of that inverter is low and the logic state of the second inverter can only be changed when the coupling of that inverter is high. One of more of the asymmetric response latches may be configured into a memory cell having complete immunity, which protects information rather than logic states.
Type:
Grant
Filed:
November 15, 1991
Date of Patent:
April 26, 1994
Assignee:
The United States of America as represented by the United States Department of Energy