Abstract: According to one embodiment of the invention, a method for discovering the presence of at least one source and target mobile device, automatically displaying a graphical interface to show the dataset from the source mobile device, and initiating the transmission of data between the mobile devices, is provided. The method further includes automatically receiving the dataset from the source mobile device, where the dataset is at least a representation of the data on the source device. In one embodiment, the representation is a subset of the data on the device and/or a description of the data on the mobile device. In another embodiment, a method for a navigation system to discover the presence of at least one mobile device, to automatically receive data from the mobile device, and to process the data with navigation operations, is provided.
Type:
Grant
Filed:
September 15, 2008
Date of Patent:
February 16, 2010
Assignee:
Intel Corporation
Inventors:
Muralidharan Sundararajan, Vinod Balakrishnan, John J. Light, Trevor A. Pering, Roy Want
Abstract: Method and apparatus are described for a memory cell includes a substrate, a body extending vertically from the substrate, a first gate having a vertical member and a horizontal member and a second gate comprising a vertical member and a horizontal member. The first gate is disposed laterally from the body and the second gate is disposed laterally from the first gate.
Abstract: Various embodiments directed to managing a call connection are described. In one or more embodiments, a call management module may retrieve a network address associated with a telephone number, initiate a first call connection using the network address from a call terminal, determine whether the network address is valid by converting the telephone number into a uniform resource identifier (URI) and sending the URI to an Authoritative Directory (AD) server for validation, and complete the call connection in accordance with the determination. Other embodiments are described and claimed.
Abstract: Systems and methods of overheat detection provide for generating a control signal on a die containing a processor based on an internal temperature of the processor and a control temperature threshold. It can be determined whether to generate a warning temperature event on the die based on a behavior of the control signal. In one embodiment, the warning temperature event provides for initiation of an automated data saving process, which reduces the abruptness of conventional warning temperature shutdowns. Other embodiments provide the user the option of saving his or her work before a shutdown temperature threshold is reached.
Abstract: A system, apparatus, method and article to perform buffering techniques are described. The apparatus may include a buffer having a fixed number of storage slots that store reconstructed picture representations received from an image processing module. Also, the apparatus may include a buffer status unit to store a multiple information items to indicate one or more buffer characteristics of the buffer. Further, the apparatus may include a buffer control module to manage storage within the buffer.
Abstract: Embodiments to perform improved error control using packet fragments are described. The apparatus may include a padding module to add a pad byte to uneven packet fragments of a packet, a partial checksum generator module to generate a partial error control value for each packet fragment, a pseudo-header generator module to generate a pseudo header for the packet, and a partial checksum combiner module to combine the partial error control values into an error control value. Other embodiments are described and claimed.
Abstract: A method, system, and apparatus to enable at least one active core in a multi-core processor to operate at a higher operating point while at least one other core in the multi-core processor is in an idle state. When the idle core exits the idle state, the operating point may be reduced after a hysteresis timer has expired.
Type:
Grant
Filed:
June 28, 2006
Date of Patent:
January 19, 2010
Assignee:
Intel Corporation
Inventors:
Jose Allarey, Varghese George, Sanjeev Jahagirdar, Oren Lamdan
Abstract: An apparatus, system, method, and article for shuffling video information are described. The apparatus may include a media processing node to receive video information. The media processing node may include a shuffling module to shuffle the video information according to a shuffle order and a trusted entity programmed based on the shuffle order to provide access to the video information. The video information may be provided in an unshuffled manner when accessed through the trusted entity. Other embodiments are described and claimed.
Abstract: Techniques to process packets for a wireless network are described. Such techniques may include determining whether a packet received by a radio network controller (RNC) includes control information or payload information. If the packet includes control information, it is sent to a slow path processing module (SPPM). However, if the packet includes payload information, it is sent to a fast path processing module (FPPM).
Abstract: A wireless device incorporates a nonvolatile memory that dynamically controls a swapping or mapping of bit pairs for a selected memory region to optimize programming times.
Abstract: An EAS/EXPULSION DETRIMENTAL SUBSTANCE tag in which the tag is held to an article by an attaching assembly, a part of which may be releasably prevented from being withdrawn from the body of the tag. The tag body may be provided with an arcuate channel through which an arcuate detacher probe can be guided for releasing the attaching assembly part. A spring clamp may provide the releasable preventing function and may include jaws specifically adapted to respond to in-plane torsional and/or other forces provided by the arcuate probe, which may be moved through the arcuate channel by rotation to reach the spring clamp. An abutment may be placed within the arcuate channel to prevent a relatively rigid wire formed into an arcuate shape from being used to release the attaching assembly part. The Benefit Denial (Ink portion) of this tag may feature an ink vial that may be disposed inside of a rubber bladder, which may then be placed in a completely sealed, ultrasonically welded compartment.
Type:
Grant
Filed:
February 5, 2007
Date of Patent:
December 15, 2009
Assignee:
Sensormatic Electronics, LLC
Inventors:
John L Lynce, Franklin H Valade, Krystyna E Cwik, Craig R Szklany
Abstract: Various embodiments directed to a cascading a network apparatus for scalability. In one or more embodiments, an apparatus may comprise an extensible markup language (XML) device to receive a content based message comprising a header, a destination Internet Protocol (IP) address, and destination port number via one or more received packets. The XML device may have a configuration and process the content based message only if the received packets comprise a destination IP address and destination port number that match the configuration of the XML device. The XML device may forward processed content based message via one or more packets that differ from the received packets. Other embodiments are described and claimed.
Abstract: A system, apparatus, method and article for high definition audio modems are described. The apparatus may include a communications path comprising a communications bus and buffers, a codec to couple to the communications bus, and a processor to couple to the communications bus. The processor may be arranged to execute instructions for a software modem to determine a round trip delay value for a communications path, and adjust the round trip delay value by varying input to one of the buffers. Other embodiments are described and claimed.
Abstract: Method and apparatus are described for a memory cell includes a substrate, a body extending vertically from the substrate, a first gate having a vertical member and a horizontal member and a second gate comprising a vertical member and a horizontal member. The first gate is disposed laterally from the body and the second gate is disposed laterally from the first gate. The horizontal member of the first gate overlaps the horizontal member of the second gate.
Abstract: A voltage regulator architecture for an integrated circuit is described. An apparatus may comprise a power switch array having multiple pass transistors, a voltage regulator array having multiple voltage regulators each coupled to a subset of the pass transistors, a subsystem circuit array having multiple subsystem circuits each coupled to a subset of the pass transistors, and a power management control unit coupled to the pass transistors and the voltage regulators. The power management control unit may be arranged to control the pass transistors and voltage regulators to provide different amounts of power to the subsystem circuits. Other embodiments are described and claimed.
Abstract: An apparatus, system, method, and article for non-volatile memory buffering are described. The apparatus may include a data storage manager to store a data item in a rewritable non-volatile memory buffer. The data item may have a file size less than or equal to a threshold value. The rewritable non-volatile memory buffer may include one or more rewritable memory regions configured to store the data item. Other embodiments are described and claimed.