Abstract: A method and apparatus for encapsulating an application tool into a computer-aided software development system that includes a number of standard software development tools. The application tool is integrated into the software development system without modification of its code. An interface description file that defines desired operations in responding to predefined events received from the development tools and from a user interface is complied to generate a symbol table and a statement table. The symbol table and the statement table are evaluated to generate objects which define operations that are performed when responding to the predefined events. An event handler responds to the predefined events received from the development tools and from the user interface by evaluating objects corresponding to the predefined events and executing the operations defined therein. Notifications received from the development tools can be utilized to trigger predefined operations by the application tool.

Abstract: Additional memory for holding marking tags is used for providing additional information regarding states acquired by an emulator during tracing for dequeueing. The marking tags are determined according to a predetermined coding scheme, loaded in a marking memory, and acquired during tracing along with the fetched instruction states. The combination of addresses, data, status, and the additional marking tags is converted into a list of states which correspond to the test program executed by the target processor means.

Abstract: A plural channel indirect digital to analog converter. Words containing address bits and data bits are received on an input and entered into a specific one of the converter channels under control of the address bits of the word. The data bits are applied to a binary rate multiplier of the channel which generates a pulse modulated output signal representing the binary value of the received data bits. The pulse modulated output signal is applied to an associated filter which converts the pulse modulated signal to an analog output signal whose amplitude represents the binary value of the received data bits. Gating circuitry ensures that each output pulse is of a precisely controlled pulse width. One of the converter channels is used to calibrate the output level of the filters. The number of data bits applied to the different channels may need not be the same and may vary in number from a minimum of 1 to a maximum of m.

Abstract: A memory mapper for an emulation system suitable for a microprocessor-based system for any size microprocessor is disclosed which uses function code comparators, range comparators, and offset values for individual mapping definitions, thereby providing faster mapping of emulation memory with higher resolution and flexibility in making changes. A single mapper cell is used for implementing each separate mapping definition. The function code comparator for the mapper cell defines the type of memory, the range comparator defines the section of memory covered by the mapper definition, and a translator is used to translate the original address to a translated address by adding an offset to the original address. Original addresses which do not match any mapper cell definitions are mapped according to a default definition.

Abstract: Apparatus for generating trigger signals for a serial stream of bits which has continuously repeating patterns and which has been formed by serializing a plurality of parallel streams, for example, a maximal length PRBS. The apparatus operates by identifying with which parallel stream cycle a trigger signal should occur and with which bit of the parallel stream in that cycle the trigger signal should be associated. Embodiments constructed in accordance with the invention can operate mainly at the clock rate of the parallel streams, that is, the lower clock rate.

Abstract: An arrangement is provided for selectively accessing and testing a digital telecommunications circuit (1) without detriment to the integrity of a signal carried thereby. The arrangement comprises an access unit (10) inserted in the circuit (1) to be tested, and test equipment (11) connected to the access unit (10) and through which the circuit to be tested can be selectively routed. The test equipment (11) includes a shift register (24) in its test circuit path. In order to match the delay introduced by the shift register (24) in the test circuit path, a similar clocked delay (21) is included in the access unit in the route followed by the telecommunications circuit (1) when undiverted. This delay matching avoids signal loss or repetition when switching the circuit to be tested between its undiverted and diverted paths.

Abstract: A non-intrusive channel-impairment analyzer is provided for measuring at least one quasi-static impairment characteristic of a band-limited data communications channel. The analyzer comprises a data receiver section and a measurement section. The data receiver section is arranged to receive data modulated onto quadrature phases of a carrier signal in two quadrature forward processing paths. The receiver section includes a data recovery circuit for effecting a decision as to the identity of the original data on the basis of the outputs from said processing paths, and decision-directed compensation means disposed in said paths and arranged to compensate for channel-impairment effects on the received signal. The measurement section is responsive to signals generated in the receiver section during the receipt of random data, to derive a measurement of at least one said channel impairment, such as phase or amplitude jitter.

Abstract: A windowed portion of a displayed waveform under test, typically from an oscilloscope display, is simultaneously displayed at a higher resolution by using a software program in conjunction with the existing timebase circuit rather than using a second timebase circuit. The software uses the resolution of the interpolators (a stretcher circuit which uses capacitors to hold acquire a charge and measure the amount of time necessary to slowly discharge the circuit) to carry through all the plotting of points to a first and second display.

Abstract: Error rates above a given threshold are detected by initiating a counter to count a group of n bits on each occurrence of an error bit. The counters are inspected on each occurrence of an error to see whether the counter initiated x error bits earlier is still counting. If the counter is still counting the error rate is above a threshold of x error bits in a group of n bits in a serial stream.

Abstract: Pulse modulation circuitry which receives n binary data bits and generates a rate/width pulse modulated signal representing the binary value of the received data bits. The lower order m of the n bits generate a rate modulated signal having a number of pulses equal to the binary value of the m bits. The remainder of the n bits width modulate the rate modulated pulses. Each least significant bit increase in the binary value of the received date bits increases the width of a rate modulated pulse by a predetermined amount.

Abstract: A detector circuit for detecting a state change of an unknown binary signal has a control circuit generating two pulse sequences which are shifted in time against each other and two flip-flops. The first pulse sequence activates the first flip-flop and clears the second one, whereas the second pulse sequence activates the second flip-flop and clear the first one. Therefore, the two flip-flops are prepared to trigger on transitions of the unknown binary signal to be tested alternatingly. Such a detector circuit can be used to avoid undue restrictions caused by the necessary recovery time of a single flip-flop.

Abstract: The low distortion drive amplifier of the present invention uses an emitter follower circuit to drive a low impedance load such as a transmission line. A constant current source is connected to the emitter terminal of the emitter follower transistor to provide a constant current through the emitter of the emitter follower circuit. Compensation circuitry is provided to offset any load current that is diverted from the emitter follower circuit to the load thereby insuring a constant current through the emitter of the emitter follower transistor. In this fashion, even with a low impedance load, a constant gain and a relatively constant output impedance can be obtained for this amplifier circuit thereby providing a low distortion drive circuit for the low impedance load such as a transmission line.

Abstract: The precision infrared position detector apparatus uses an information display device that has a substantially cylindrical shaped screen to limit curvature of the screen to a single dimension. In addition, to compensate for this curvature, a flexible printed circuit board is used to align the row of infrared light sources and detectors along the same curvature as the screen of the information display device. A first flexible printed circuit board is equipped with a single row of infrared light sources while a second flexible printed circuit board is equipped with a signal row of corresponding infrared light detectors. A frame member is used to bend the flexible printed circuit board into a substantially cylindrical shape that matches the curvature of the screen of the information display device.

Abstract: A plurality of data transmitting and receiving devices (1) are inter-connected by an interface bus system configured as two or more sub-bus systems (2,3,4) connected into a chain by a corresponding number of communication links (5). Each sub-bus system (2,3,4) includes a communications arrangement (7) interfacing the sub-bus system with the associated link or links (5). The overall interface bus system operates in accordance with a data transfer protocol that involves a handshake procedure requiring the participation of all active devices (1) connected to the bus system. In order to avoid the whole installation locking up upon one sub-system (3,4) becoming non-responsive, each communication arrangement (7), other than the one associated with the last sub-bus system (4) in the chain, is arranged to check the responsiveness of its down-chain neighbour when requested to do so by a control input from the installation controller (1A).

Abstract: A clock signal generator is based on a phase locked loop arrangement. The loop includes an adjustable divider. The reference signal for the loop is applied to another adjustable divider. This allows the generation of a wide range of frequencies by appropriate selection of the division ratios.

Abstract: Method and apparatus for achieving unlimited and variable presistence in a digital oscilloscope having a samplier, analog-to-digital converter, high speed memory, microprocessor, linked list memory, display memory with bits corresponding to pixels on a raster display screen and hardware for refreshing the screen from memory. Variable persistence controls the length of time waveform data persists on a display. Waveform data persists indefinitely with unlimited persistance. For unlimited persistence, analog data is acquired by the sampler, converted to digital, stored in high speed memory, converted to coordinates corresponding to appropriate pixels, and corresponding display memory bits are set. For variable persistence, linked lists are maintained for each column on the display screen, each link containing a row coordinate and time remaining before erasing variable.

Abstract: Time modulation in a vector film recorder is used to control the color of an image to be recorded by using a constant intensity electron beam and controlling the number of electron beam sweeps for each primary color in a color filter wheel and for each vector in a set of vectors which when summed make up the image to be recorded.

Abstract: This invention provides a polar device measuring apparatus which can bias a device under test in a proper polarity. The measuring apparatus is computer-controlled and automatically selects the polarity of the bias voltage based on the measured value of voltage across the device.

Abstract: An NMOS analog voltage comparator is disclosed having two matching cascaded inverter-pairs. The comparator has fast response time, is not sensitive to temperature variations while operating, and operates independent of integrated circuit parameter variations encountered during circuit manufacture.

Abstract: A modification of a woven cable (wire and fabric woven together to form a flat ribbon cable) assembly, in which the signal wires of the transmission lines are replaced with solderable resistance wires, thereby providing an economical method of building multiple lossy transmission lines.