Abstract: A device for testing flat panel displays includes an interface having compliant bumps mounted thereon, which make electrical contact with pads on the display panel. The interface may have a hole formed therein for allowing the passage of light therethrough when the interface is mounted on the display panel. The compliant bumps ensure that all of the bumps make sufficient electrical contact with the pads.

Abstract: Device configuration processes operated within an operating system are run in parallel up until one or more new devices are detected. Once that occurs, the configuration process waits for current running processes to complete without starting new ones, and then re-runs the configuration processes needing to define new devices in the order they would have run if the entire operation had been performed serially. As a result, since most configurations processes will not be detecting new devices, they will run all the way to completion in parallel with others, thereby reducing system boot times. However, if a new device is discovered, it will be assigned the correct name with respect to the other devices.

Abstract: A Self-Timed CMOS Static Circuit Technique has been invented that provides full handshaking to the source circuits; prevention of input data loss by virtue off interlocking both internal and incoming signals; full handshaking between the circuit and sink self-timed circuitry; prevention of lost access operation information by virtue of an internal lock-out for the output data information; and plug-in compatibility for some classes of dynamic self-timed systems. The net result of the overall system is that static CMOS circuits can now be used to generate a self-timed system. This is in contrast to existing self-timed systems that rely on dynamic circuits. Thus, the qualities of the static circuitry can be preserved and utilized to their fullest advantage.

Abstract: A pulsed lamp is supplied wherein electrons are supplied from a substantially flat cold cathode having low effective field emission work function and are accelerated to excite light emission from a phosphor layer on a transparent anode plate. The emission site density of the cathode and emission current characteristics vs electric field are selected to provide high light output while requiring only small duty cycle pulses from a voltage generator.

Abstract: Data stream touch instructions are software-directed asynchronous prefetch instructions that can improve the performance of a system. Ideally, such instructions are used in perfect synchronization with the actual memory fetches that are trying to speed up. In practical situations, it is difficult to predict ahead of time all side effects of these instructions and memory access latency/throughput during execution of any large program. Incorrect usage of such instructions can cause degraded performance of the system. Thus, it is advantageous to measure the performance of such instructions.

Abstract: A carbon film having an area of insulating material surrounded by an area of conducing material, and an area of material between the area of insulating material and the area of conducting material having a graded dielectric constant which varies from high to low from the area of insulating material to the area of conducting material.

Abstract: A data processing system including a processor having a load/store unit and a method for correcting effective address aliasing. In the load/store unit within the processor, load and store instructions are executed out of order. The load and store instructions are assigned tags in a predetermined manner, and then assigned to load and store reorder queues for keeping track of the program order of the load and store instructions. A real address tag is utilized to correct for effective address aliasing within the load/store unit.

Abstract: An ISYNC instruction does not cause a flush of speculatively dispatched or fetched instructions (instructions that are dispatched or fetched after the ISYNC instruction) unconditionally. The present invention detects the occurrence of any instruction that changes the state of the machine and requires a context synchronizing complete; these instructions are called context-synchronizing-required instructions. When a context-synchronizing-required instruction completes, the present invention sets a flag to note the occurrence of that condition. When an ISYNC instruction completes, the present invention causes a flush and refetches the instruction after the ISYNC if the context-synchronizing-required flag is active. The present invention then resets the context-synchronizing-required flag. If the context-synchronizing-required flag is not active, then the present invention does not generate a flush operation.

Abstract: An algorithm for efficient restructuring of logic circuitry to improve selected characteristics (delay and/or area). Along a path through the logic circuitry, the logic is converted to equivalent implementations with the same Boolean function using specific choices from the library of available cells, such that these conversions provide an improvement in the cost/benefit for the selected characteristics.

Abstract: A data processing system and method for prefetching data in a multi-level code subsystem. The data processing system includes a processor having a first level cache and a prefetch engine. Coupled to the processor are a second level cache, and a third level cache and a system memory. Prefetching of cache lines is concurrently performed into each of the first, second, and third level caches by the prefetch engine. Prefetch requests from the prefetch engine to the second and third level caches are performed over a private or dedicated prefetch request bus, which is separate from the bus system that transfers data from the various cache levels to the processor. A software instruction or hint may be used to accelerate the prefetch process by overriding the normal functionality of the hardware prefetch engine.

Abstract: A data processing system includes a processor having a first level cache and a prefetch engine. Coupled to the processor are a second level cache and a third level cache and a system memory. Prefetching of cache lines is performed into each of the first, second, and third level caches by the prefetch engine. Prefetch requests from the prefetch engine to the second and third level caches is performed over a private prefetch request bus, which is separate from the bus system that transfers data from the various cache levels to the processor. The prefetch request may include a signal notifying the third level cache to also prefetch.

Abstract: A plurality of field emission device cathodes each generate emission of electrons, which are then controlled and focused using various electrodes to produce an electron beam. Horizontal and vertical deflection techniques, similar to those used within a cathode ray tube, operate to scan the individual electron beams onto portions of a phosphor screen in order to generate images. The use of the plurality of field emission cathodes provides for a flatter screen depth than possible with a typical cathode ray tube.

Abstract: A keyboard is placed into a suspend mode. Upon the detection of the pressing of a key, the keyboard processor is wakened from the suspend mode. No power is consumed during the suspend mode, sine the keyboard processor is not scanning the key matrix. The key matrix drive circuitry may also be tested by monitoring a signal emanating from the key matrix drive circuitry and scanning each of the drive lines in the key matrix. If the signal is altered, then the associated drive line in the keyboard drive circuitry is defective. Testing of sense circuitry is performed by changing pull-up resistors to pull-down resistors and then reading sense lines.

Abstract: A device for testing flat panel displays includes an interface having compliant bumps mounted thereon, which make electrical contact with pads on the display panel. The interface may have a hole formed therein for allowing the passage of light therethrough when the interface is mounted on the display panel. The compliant bumps ensure that all of the bumps make sufficient electrical contact with the pads.

Abstract: A plurality of field emission device cathodes each generate emission of electrons, which are then controlled and focused using various electrodes to produce an electron beam. Horizontal and vertical deflection techniques, similar to those used within a cathode ray tube, operate to scan the individual electron beams onto portions of a phosphor screen in order to generate images. The use of the plurality of field emission cathodes provides for a flatter screen depth than possible with a typical cathode ray tube.

Abstract: A system and method for allowing operation of a storage array after a failure within a set of an n-way set associative cache includes determining that there is a failure in a bit line in the storage array, setting a flag to inhibit access to the portion of the array accessed by the failing entity and storing and retrieving data from remaining portions of the array. The present invention is well adapted for use with n-way set associative cache storage arrays.

Abstract: A reduced dispersion optical waveguide and methods of fabricating the same are implemented. The optical waveguide may be fabricated in commercially practicable units without having to predetermine its length in a particular application. The reduced dispersion optical waveguide prevents optical pulse overlap in optical waveguide transmission systems operating over long distances or at high data rates.

Abstract: A testing methodology for increasing the performance and reliability of integrated circuits (“chips”) outputted from a manufacturing process, utilizes a method by which the operating frequency of the integrated circuit is measured when the Self-Timed Pulse Control parameter is adjusted to provide a more strict test upon the chip. Under this more stringent test, the integrated circuits that do not pass the test then are designated as failures or marketed with listed lower operating frequencies.

Abstract: Parametric test data is taken on a sampled set of a particular integrated circuit (IC) using both an Automatic Test Equipment (ATE) tester and a system test motherboard. The parametric test data comprises maximum operating frequency, maximum operating temperature and minimum operating power supply voltage. A maximum operating frequency is determined at a particular fixed operating temperature and power supply voltage. A maximum operating temperature is determined at a particular fixed operating frequency and power supply voltage. Finally, a minimum operating power supply voltage is determined at a particular fixed operating frequency and temperature. Multiple two parameter graphs are plotted and the slope or numerical derivative for each plot is calculated as conversion factors. During a normal production run for the particular IC performance limit data is taken on the ATE tester comprising the same three parameters of maximum operating frequency at a particular temperature and power supply voltage.