Abstract: Within a data processing system implementing L1 and L2 caches and stream filters and buffers, prefetching of cache lines is performed in a progressive manner. In one mode, data may not be prefetched. In a second mode, two cache lines are prefetched wherein one line is prefetched into the L1 cache and the next line is prefetched into a stream buffer. In a third mode, more than two cache lines are prefetched at a time. In the third mode cache lines may be prefetched to the L1 cache and not the L2 cache, resulting in no inclusion between the L1 and L2 caches.
Type:
Grant
Filed:
August 23, 1995
Date of Patent:
April 14, 1998
Assignee:
International Business Machines Corporation
Inventors:
Michael John Mayfield, Trinh Huy Nguyen, Robert James Reese, Michael Thomas Vaden