Abstract: Method of scheduling execution of transmit-side and receive-side procedures by a single processor in a full-duplex modem. Buffers of minimal size are employed in conjunction with the processor to guarantee no errors in the signal processing procedures. In one embodiment, transmit-side procedures are given priority so that if a transmit-enable signal is received, a receive-side procedure being executed by the processor is interrupted to allow execution of the transmit-side procedure. This priority is most useful because transmit-side procedures execute more rapidly than do receive-side procedures.

Abstract: A data link controller (DLC) 52 is disclosed which employs buffers (100,106) on both receive and transmit sides. These last-in, first-out buffers contain a position indicating that a character is the last one of a packet. In this way, a user need not monitor reception or transmission on a character-by-character basis, but need only concern themselves with packets. The receive and transmit FIFO's generate requests for more characters by monitoring the number of characters stored and thereby automatically receive and transmit characters without processor intervention. A four-stage mechanism (600,602,604,606,608,610,612,614) permits monitoring of multiple contiguous frames (back-to-back frames) received. Control of the DLC is provided by status and control registers (112,212) which are accessible to the user via a microprocessor interface (50).

Abstract: Method and apparatus is disclosed which disables which disables a repeater connected to a packet-based network so that improper symbols are not propagated. A communications management unit employing the invention would, upon reception of an improper symbol, cause transmission to halt. The invention implements a three-state machine. Reception of any improper symbol, or symbol with a parity error, causes entry into a forced-halt state. Reception of an IDLE symbol causes transition to a forced-idle state. Return to the start state occurs upon reception of a start-of-packet symbol pair.

Abstract: Method and apparatus are disclosed providing selective amplification of signals whereby signals exceeding a threshold voltage are amplified while signals below the threshold voltage are attenuated. The invention is preferably employed in a receiver of signals on an ISDN and reduces errors in the first data bit following framing bits. Furthermore, noise components in the received signals are attenuated. An operational amplifier (28) has an amplification determined by the ratio of a feedback resistance (30) to an input resistance. The input resistance consists of a first resistor (26), and a second resistor (24), which can be selectively placed in series with the first resistor. A pair of series-connected diode pairs (16, 18, 20, 22) are connected in parallel with the second resistor. One pair of series-connected diodes oriented oppositely to the other pair. The forward-biased saturation voltage of the series-connected pairs of diodes determine the threshold voltage of the non-linear amplifier.

Abstract: A dual port timing controller (DPTC) (56) in conjunction with an interprocessor communication register (596) provides a shared random access memory (S-RAM)(22a). The S-RAM can be accessed either by a local processor (18) or a host processor (595) which, in a preferred configuration, controls an integrated circuit integrated services data protocol controller. The DPTC provides control signals allowing an ordinary RAM to be operated as an S-RAM. The DPTC includes a semaphore register (596) that stores bidirectional interprocessor interrupts, enabling passing of high level messages between the local and host processors.

Abstract: A multiplier formed as a single integrated circuit chip generates in consecutive clock cycles the single-precision partial products of multiple-precision operands. Provision of an on-chip temporary register and "wrap-back" path avoids transmitting and externally storing intermediate results so that no clock cycles are used solely for data-transfers or other "overhead". Consecutive double-precision multiplications can be performed concurrently so that complete quadruple-precision products are generated every four cycles.

Abstract: A one-chip, integrated-circuit, 32-bit bipolar arithmetic-logic unit (ALU) capable of performing complex operations on selected one, two, three, or four 8-bit bytes or selected contiguous bits of the operands in a single clock cycle. The ALU has three 32-bit inputs consisting of two data word operands and a mask; operand with shifters provided at one of the operand input, the mask input and at the ALU output so that three operands can be simultaneously received, shifted, masked, combined, and the result shifted in a single instruction cycle. Bit positions which are not selected to take part in an ALU operation pass unaffected to the outputs from one of the data word inputs. A swap multiplexer is present at the data word inputs to afford interchanging of these inputs before processing by the ALU.

Abstract: An instruction processor suitable for use in a reduced instruction-set computer employs an instruction pipeline which performs conditional branching in a single processor cycle. The processor treats a branch condition as a normal instruction operand rather than a special case within a separate condition code register. The condition bit and the branch target address determine which instruction is to be fetched, the branch not taking effect until the next-following instruction is executed. In this manner, no replacement of the instruction which physically follows the branch instruction in the pipeline need be made, and the branch occurs within the single cycle of the pipeline allocated to it. A simple circuit implements this delayed-branch method. A computer incorporating the processor readily executes special-handling techniques for calls on subroutine, interrupts and traps.

Abstract: A high speed register file for use by an instruction processor suitable for reduced instruction-set computers (RISCs) is disclosed which is preferably used with an efficient register allocation method. The register file facilitates the passing of parameters between procedures by dynamically providing overlapping registers which are accessible to both procedures. Each procedure also has a set of "local" registers assigned to it which are inaccessible from other procedures. The register file is divided into a number of blocks and a protection register stores a word which proscribes access by a particular procedure or task to certain blocks. In this manner, an instruction processor using the register file can operate on multiple tasks maintaining the integrity of each from undesired changes occuring in the others.

Abstract: Method of detecting the INFO 1 signal pattern which avoids false activation of a data transmission line caused by noise on the line. An initial line sampling rate four times the nominal 192 kbs line rate is used to detect a HIGH mark to avoid the difficulties resulting from sampling right at the edge of a mark. Subsequent sampling is done at the nominal line rate to detect two opposite polarity marks out of every consecutive eight-bit time periods. If six consecutive eight-bit time periods are detected, each having its HIGH and LOW marks in the same relative positions, the line is activated. The method is readily implemented as a set of three "state machines" and consequently can be constructed from programmable logic arrays.

Abstract: For each channel, a pair of buffers permits "non-slip" transfer of data signals on and off a bus synchronized with signals on a time-division multiplexed pulse-code modulation (PCM) highway. A source buffer consisting of a serial-in, parallel-out register and two parallel-in, parallel-out registers receives signals from one of the PCM channels and transmits these signals onto a bus synchronized with a data-routing multiplexer employed within a digital exchange controller employing the device. A destination buffer consisting of two parallel-in, parallel-out registers and a parallel-in, serial-out register receives signal from the bus and, in conjunction with a transmit multiplexer, generates the signals on the PCM highway.

Abstract: A bounds checker consisting of a pair of comparators that each compare a 16-bit number with a lower and an upper limit stored in registers. The device is preferably constructed as a single integrated circuit chip employing emitter coupled logic (ECL) circuitry and can be made externally compatible with either transistor transistor logic (TTL) circuitry or ECL circuitry. The device can be cascaded to operate on extended-precision numbers and has a pin which can be used to select comparison of numbers either as signed two's complement numbers or as unsigned numbers. No added gate delay is imposed by the device's ability to operate either type of number.

Abstract: A single-chip microprogrammable sequence controller includes a subroutine stack and conditional branching facilities. The controller performs a test and mask operation followed by comparison with a user-defined constant to effect a Boolean sum-of-product function. Address control logic includes a flag signal set by compare logic; the flag is available to a microinstruction decoder where it can be used during a subsequent conditional branch operation based on the setting of the flag.

Abstract: A compact rectangular parallel multiplier array of Booth summation cells includes along a left edge a cell which reduces to two the number of sign-extension bits sufficient to generate subsequent intermediate products. The cell employs optimized logic circuitry which generates a sum, a carry and a guard bit for use during generation of the next most-significant intermediate product.

Abstract: Method and apparatus for rapid, low-jitter acquisition of a clock signal at a serial communication port. In the absence of communication over the port, and during clock acquisition, a free-running clock is generated for local communication. Following clock acquisition by a circuit which performs coarse phase adjustments, a simple logic network generates refined phase adjustment signals which drive a variable, nominal divide-by-32, counter so that the clock generated thereby is smoothly brought into synchronization with the acquired clock in one bit increments. In a typical application, at most 48 bit periods at the port are required to synchronize the clock, with a clock phase jitter of less than 1.1%.

Abstract: A multiplexer for use in a digital subscriber controller having a number of analog ports and digital ports which can be programmed via an external microprocessor to establish time-division multiplexed bidirectional data paths between three subscriber-selected ports designated as "sources" and three subscriber-selected ports designated as "destinations". Among the ports is a line-interface port having two 64 kilobit-per-second channels on which analog/digital data is received from and transmitted onto the network transmission line. Among the digital ports is a three-channel serial port and a two-channel microprocessor interface port. An analog port is also provided at which a variety of audio transducers may be connected.

Abstract: Method and apparatus suitable for inclusion in an integrated circuit transceiver meeting IEEE 802.3 standards which detects "collisions" so that more than one station will not simultaneously transmit over a network. The method employs a novel three-pole cyclical low-pass filter which attenuates the ac component received over the network to less than 20 mV to allow collision detection within the 900 nanosecond budget allowed by the IEEE standard. A differential operational amplifier receives the signal from the network and a collision reference voltage. The signal generated by the differential amplifier is filtered by the low-pass filter and then coupled to a high-gain comparator which acts as a zero-crossing detector. The comparator generates ECL logic signals representing the occurrence or non-occurrence of a collision. The resulting collision detector operates over a wide range without the need for field "trimming".

Abstract: A simple architecture to implement a mechanism for performing data references to storage in parallel with instruction execution. The architecture is particularly suited to reduced instruction-set computers (RISCs) and employs a channel address register to store the main memory load or store address, a channel data register which temporarily stores the data from a store operation and, a channel control register which contains control information including the number of the register loaded within the file, in the case of a load operation. This number is used to detect instruction dependency of the data to be loaded. Logic circuitry suspends further instruction processing if the data required from a load is not yet available. A data-in register is used to store load data until an instruction execution cycle is available for writing it back to the register file. Logic circuitry detects storage of data prior to its writing back, so as to effectively replace the register file location.

Abstract: A single-chip microprogram sequence controller can be selectively operated in either an interrupt mode or a trapped mode. In the interrupt mode, the miroprogram sequencer allows the currently-executing microinstruction to finish execution before beginning the interrupt routine which services the asynchronous event which requested the interruption of the presently-executing microinstruction stream. In the trap mode, the sequencer aborts the currently-executing microinstruction to avoid an irreversible error which would result if the microinstruction were to finish execution before beginning the routine which services the event which requested trapping of the presently-executing microinstruction.

Abstract: An all-digital signal processor (DSP) is disclosed which performs pulse code modulation (PCM) coding and decoding (CODEC) filter operations for both received and transmitted signals, among other functions. A user can access various programmable registers via the microprocessor to specify parameters used in the execution of programs by the DSP. Two 19-bit wide bidirectional data busses are provided for time-division multiplexed communication between various elements, which include a random access memory (RAM), an arithmetic-logic unit (ALU), and an interface to a receive-side analog-to-digital (A/D) converter and a transmit-side digital-to-analog (D/A) converter. A programmed logic array (PLA) executes microcode which controls the processing of signals by the ALU section. A variety of other operations can be performed under control of the PLA such as generation of dual-tone multi-frequency (DTMF) signals commonly used in telecommunications.