Abstract: A system and process for efficiently determining absolute addresses for an intermediate code model of an address space are described. A processor interfaces to a main memory comprising a plurality of addressable locations. Each such addressable location is referenced by an absolute address having a maximum size directly proportional to the total number of the addressable locations in the main memory. The absolute addresses form the address space. Source code is supplied specifying program routines which each include at least one reference to an absolute address within the address space. A translator interfaces with the main memory and the storage device. Object code is generated from the source code program routines. Each such absolute address reference in the source code program routines is instantiated with a code sequence for referencing a subset of the address space.

Abstract: Offset between a pair of images is determined using parallel processing techniques in a general-purpose digital serial processor. For each each image, a patch of pixels is selected and convolved with a Laplacian kernel. The result is convolved with a Gaussian kernel in each of the x- and y-directions to produce a registration image. The registration images are binarized, bit-packed, and correlated to one another by performing an EXOR operation for each pixel location at each of a plurality of relative offsets of the images. The results of the EXOR operation are summed to produce an image-correlation value for each relative offset. The image-correlation indicating highest correlation determines relative offset of the images. The determined offset can be used for a variety of purposes in automating control of E-beam and FIB systems, to register images to one another or to identify a location in one image which corresponds to a selected location of the other image.

Abstract: Probe-point placement methods are described. A layout description, a netlist description and a cross-reference description of an IC are retrieved from storage. The data structures associate with each net name a list of polygons. Polygons of a selected net are broken into segments of a specified step size. Each segment is evaluated in accordance with a set of prober rules. Values produced by the prober rules are weighted and combined to obtain a prober score for each segment. The prober score indicates suitability of the corresponding net location for probing. If the best prober score indicates an optimal segment exists for probing, the coordinates of that segment are stored and used to direct a probe to the corresponding location of the IC. If the best prober score indicates no optimal segment exists for probing, each segment of the net is evaluated in accordance with a set of probe-point cutter rules.

Abstract: Generation, validation and fault-grading of test patterns, and test and debug of logic circuits, are enhanced by emulation of the logic circuits in programmable gate arrays. Two emulations of the logic circuit are preferably created, one of which is a "good" model containing no faults and the other of which is a "faultable" model into which possible faults may be selectively introduced. A fault is introduced in the faultable model, and the two models are exercised in parallel by applying the same pattern of test vectors to both models. The test vector pattern may be generated by an emulation of the intended operating environment of the logic circuit. Differences in the output signals of the two models indicate that the fault has been detected by the applied test pattern. Application of the test pattern is repeated for each of a sequence of possible faults, to determine the extent to which the test pattern enables detection of faults in the logic circuit.

Abstract: Driver circuits are provided which also serve as termination and clamp in an IC tester. When it is to drive a port of a device under test (DUT) between two predetermined voltage levels, the driver's I/O terminal is switched between two predetermined voltage levels with an output impedance that matches the transmission line between the driver circuit and the DUT. When the DUT's port is supplying an output signal, the driver circuit can be programmed to provide one of two types of termination. If the DUT's port is specified as capable of driving the load, the transmission line between the driver circuit and the DUT is terminated by switching the driver circuit's I/O terminal to a predetermined voltage level with an impedance of Z.sub.0. If the DUT's port is not specified as being capable of driving such a termination load, the driver circuit functions like a Z-clamp circuit.

Abstract: Focused ion bean (FIB) milling through a power plane of a device to expose or cut a hidden, lower-layer conductor requires accurate positioning relative to the hidden conductor of a box defining boundaries of the FIB operation. This can in general be done by aligning surface information (topology or voltage contrast) visible in a FIB or scanning electron microscope (SEM) image with an overlay image generated from stored data describing the device. The location of the hidden conductor relative to the visible surface information is determined from the stored data. Advanced integrated circuits often do not provide enough unique surface information near the FIB operation area to align the images with sufficient accuracy.

Abstract: Methods and apparatus are disclosed for positioning the field of view in a system for IC probing or repair, where the system comprises means for supporting an IC device having multiple physical layers and multiple internal nets, and controllable positioning means for positioning the field of view relative to the device. A data set is prepared which describes each physical layer of the device as a plurality of reduced polygons. Each of the reduced polygons is associated with a physical layer of the device and with at least one net of the device. For each of a plurality of selected nets, polygons associated with the net are dilated to define the periphery of a region encompassed by the field of view when a point within the field of view is traced around the periphery of a reduced polygon. A bit plane of the dilated polygons is mapped for each net, and regions of overlap the mapped bit planes are identified.

Abstract: Focused ion beam (FIB) systems are used for IC mask or reticle repair and imaging and other applications. The impinging ions can cause an undesirable charge build-up on the specimen. Prior to beginning repair operations in a FIB system, a fluid containing a conductive material such as dimethyl ammonium salt is applied to the reticle, mask or device and allowed to dry, leaving a thin conductive layer on the specimen. A leakage path is preferably provided from the thin conductive layer to ground, to prevent charge buildup on the specimen. The FIB is used to cut through the conductive layer before commencing FIB deposition, to assure proper bonding of the deposited material. The technique also has application with electron beam imaging systems.

Abstract: An electron-beam test probe system (400) in which a pulsed laser-beam source (404) and a photocathode assembly (430) are used with an electron-beam column (426) to produce a pulsed electron beam at a stabilized repetition frequency. A pulse picker (414) allows the pulse repetition frequency of the pulsed electron beam to be reduced to a submultiple of the pulsed laser repetition frequency. A test pattern generator (416) is programmable to apply a desired pattern of test vector patterns to an electronic circuit to be probed, the test vector patterns being synchronized with the stabilized laser-beam pulse repetition frequency. A timebase circuit (412) allows the test vector patterns to be time-shifted relative to the pulsed electron beam. The electronic circuit under test can thus be probed at any desired point in the applied test vector pattern by control of the pulse picker and by time-shifting the test vector pattern.

Abstract: A surface is probed with a pulsed electron beam and secondary electrons are detected to produce a detector signal. First portions of the detector signal are substantially dependent on the voltage of the surface being probed, while second portions of the detector signal are substantially independent of the voltage of the surface being probed. In general, the first and second portions of the detector signal include unwanted noise caused by low-level sampling due to beam leakage and/or by scintillator afterglow in the secondary-electron detector. The detector signal is sampled during the first signal portions and is sampled during the second signal portions. The sampled first signal portions are combined with the complement of the sampled second signal portions to produce a measured voltage signal representing voltage of the conductor. In a preferred sampling scheme, alternate electron-beam sampling pulses are held-off.

Abstract: Methods and apparatus are disclosed for conditional acquisition of potential measurements in integrated circuits, with the aid of electron-beam probes. The conditional acquisition enables display of waveform images which permit diagnosis of the causes and/or origins of failure in circuits which fail intermittently. Data is acquired in the normal manner on each pass through the test pattern. At the end of each test pattern execution a pass/fail signal from the tester exercising the circuit is used to reject or accept the acquired data. In this fashion, it is possible to accumulate only that data which carries information about the failure of interest and to reject data which does not. Over several test pattern repetitions it is possible to display only that data which shows the failure. Engineers are thus able to efficiently diagnose intermittent failures without the need to change device operating parameters.

Abstract: Apparatus is provided which includes a FIB column having a vacuum chamber for receiving an IC, means for applying a FIB to the IC, means for detecting secondary charged particles emitted as the FIB is applied to the IC, and means for electrically stimulating the IC as the FIB is applied to the IC. The apparatus may be used, for example, (1) to locate a conductor buried under dielectric material within the IC, (2) for determining milling end-point when using the FIB to expose a buried conductor of the IC, and (3) to verify the repair of an IC step-by-step as the repair is made.