Abstract: In one embodiment, a first dielectric layer (32) that overlies a fuse (16) and a bonding pad (30) is etched with a first etch process. This first etch process exposes a portion (40) of a second dielectric layer (20) that underlies the first dielectric layer (32) and overlies the fuse (16). In addition, the first etch process also forms a bond pad opening (38) that exposes a portion (42) of an anti-reflective layer (28) that forms a portion of the bonding pad (30). A second etch process is then used to etch the exposed portion (42) of the anti-reflective layer (28) and the exposed portion (40) of the second dielectric layer (20) at substantially the same rate to form a fuse window (45) overlying the fuse (16). The second etch process prevents over etching of the second dielectric layer (20), and thus exposure of the underlying fuse (16).

Abstract: In one embodiment, an integrated circuit (10, 110) has a contention detection circuit (12, 112) coupled to a tri-stateable output buffer (18, 118). The contention detection circuit (12, 112) provides a contention tri-state control signal (34, 134) to the tri-stateable output buffer (18, 118) in order to place it in a tri-stated condition when an external device (31, 131), such as a computer, supplies power to an input/output pad (22, 122) on the integrated circuit (10, 110). Thus, external and/or internal buffer contention is avoided when an external device (31, 131), such as a computer, supplies power to an input/output pad (22, 122) on the integrated circuit (10, 110).

Abstract: An integrated circuit substrate (10) is uniformly coated with a defect free layer of material (18), while minimizing the volume of material (18) dispensed on to the integrated circuit substrate (10). In one embodiment a first predetermined quantity of material (18) is dispensed on to the integrated circuit substrate (10) while the integrated circuit substrate (10) is not spinning. After the first predetermined quantity of material (18) is dispensed the integrated circuit substrate (10) is radially accelerated to a first predetermined spin speed. A second predetermined quantity of the material (18) is then dispensed on to the first predetermined quantity of material (18), while the integrated circuit substrate (10) is spinning. After the second predetermined quantity of material (18) is dispensed the integrated circuit substrate (10) is radially accelerated to a second predetermined spin speed.

Abstract: In one embodiment of the invention, conductive support structures (112) are formed within an interlevel dielectric layer. The conductive support structures (112) lie within the bond pad region (111) of the integrated circuit and provide support to portions of the interlevel dielectric layer that have a low Young's modulus. The conductive support structures (112) are formed using the same processes that are used to form metal interconnects in the device region (109) of the integrated circuit, but they are not electrically coupled to semiconductor devices that lie within the device region (109). Conductive support structures (114) are also formed within the scribe line region (104) to provide support to the interlevel dielectric layer in this region of the integrated circuit.

Abstract: In one embodiment, a plurality of atomic charge pumps (52, 54, 56) are connected together in series to form a distributed charge source (24). The atomic charge pumps (52, 54, 56) are operated sequentially over time to reduce supply signal noise. In addition, the distibuted charge source (24) is compatible with low power applications because each atomic charge pump (52, 54, 56) can be independently powered down if it is not required.

Abstract: A first dielectric layer (22) is formed over a semiconductor device substrate. A resist layer (32) is then patterned to expose portions of the first dielectric layer (22). Portions of the first dielectric layer (22) are removed to expose portions of the semiconductor device substrate (42). The resist layer (32) is then removed. The semiconductor device substrate is cleaned without using a fluorine-containing solution and a second dielectric layer (62) is formed overlying the semiconductor device substrate.

Abstract: A plurality of memory tiles (22) are arranged to form a tiled memory array (12) in an integrated circuit device (400). In accordance with the present invention, each of the memory tiles (22) in the tiled memory array (12) has charge source circuitry (24) to provide the sufficient reference voltages for proper operation of the memory tile (22). In addition, each memory tile (22) may include local error detection and correction circuitry (36b). To facilitate reliable operation, each memory tile may also include redundant rows and/or columns, and appropriate redundancy control circuitry (32c′, 32c″).

Abstract: In one embodiment, a polishing apparatus (10) includes a retaining ring (12), a pressure ring (16), a first seal (18), and a second seal (20). The retaining ring (12) is movably attached to the pressure ring (16) to create a uniform pressure distribution across the retaining ring (12). In addition a positive fluid pressure is applied to the first seal (18) and the second seal (20) to create the uniform pressure distribution across the retaining ring (12). The uniform pressure distribution across the retaining ring (16) allows a semiconductor substrate (51), polished with the polishing apparatus (10), to have a reduced edge exclusion, and thus increased die yield.

Abstract: In one embodiment, an integrated circuit (10, 110) has a contention detection circuit (12, 112) coupled to a tri-stateable output buffer (18, 118). The contention detection circuit (12, 112) provides a contention tri-state control signal (34, 134) to the tri-stateable output buffer (18, 118) in order to place it in a tri-stated condition when an external device (31, 131), such as a computer, supplies power to an input/output pad (22, 122) on the integrated circuit (10, 110). Thus, external and/or internal buffer contention is avoided when an external device (31, 131), such as a computer, supplies power to an input/output pad (22, 122) on the integrated circuit (10, 110).

Abstract: In one embodiment, the reliability of an integrated circuit having a floating gate device (50), a high breakdown voltage transistor (52), and a low breakdown voltage transistor (54), which are electrically isolated from each other by a trench isolation region (12), is improved by using an oxidation resistant layer (24). The oxidation resistant layer (24) protects portions of the trench isolation region (12) when the gate dielectric layer (30) for the high breakdown voltage transistor (52) is formed, and when the gate dielectric layer (36) for the low breakdown voltage transistor (54) is formed. The oxidation resistant layer (24) minimizes etching of the field isolation region (12) so that thinning or recessing of the field isolation region (12) is minimized.

Abstract: A method for making copper interconnections in an integrated circuit is described. The structure is a damascene copper connector whose upper surface is coplanar with the upper surface of the insulating layer in which it is embedded. Out-diffusion of copper from the connector is prevented by two barrier layers. One is located at the interface between the connector and the insulating layer while the second barrier is an insulating layer which covers the upper surface of the connector. The damascene process involves filling a trench in the surface of the insulator with copper and then removing the excess by chem.-mech. polishing. Since photoresist is never in direct contact with the copper the problem of copper oxidation during resist ashing has been effectively eliminated.

Abstract: A nonvolatile memory architecture (10) contains a plurality of memory arrays (12) formed by a plurality of floating gate memory cells and supports a 1X and 2X architecture. The nonvolatile memory design contains high voltage row decoders (16), low voltage row decoders (18), data multiplexors (24) and low voltage control circuitry (22). The nonvolatile memory architecture (10) features a pipelined scheme with a 100 MHz operation. Data multiplexers (24) and sense amplifier circuitry (26) with a master/slave portion increase the data access rate.

Abstract: An integrated circuit (10) contains a central processing unit (CPU) (12) and a plurality of memory blocks (26-34) configured into one or more banks of memory. A plurality of power control switches (38-42) are used to dynamically select which of a plurality of external voltage supply signals are provided to power each of the memory blocks (26-34). The power control switches (38-42) may be configured from software via writing the data to a register (24) or can be enabled by test control circuitry (22) or can be automatically enabled in response to VDD power voltage failure. In addition, an intelligent controller can dynamically control the switches in response to execution flow of data accesses and instruction fetches from the memory banks so that only currently accessed memory banks or recently accessed memory banks are activated at a high power level while all other memory banks are in a low power stand-by mode.

Abstract: In one embodiment a non-volatile memory device having improved reliability is formed by oxidizing a first portion of a semiconductor substrate (12) to form a first silicon dioxide layer (14). The first silicon dioxide layer (14) is then annealed and second portion of the silicon substrate, underlying the annealed silicon dioxide layer (16), is then oxidized to form a second silicon dioxide layer (18). The annealed silicon dioxide layer (16) and the second silicon dioxide layer (18) form a pre-oxide layer (20). The pre-oxide layer (20) is then nitrided to form a nitrided oxide dielectric layer (22). A floating gate is then formed overlying the nitrided oxide dielectric layer (22), which serves as the tunnel oxide for the device. Tunnel oxides formed with the inventive process are less susceptible to stress-induced leakage, and therefore, devices with improved data retention and endurance may be fabricated.

Abstract: An interconnect structure having a dielectric layer with low dielectric constant is formed within an integrated circuit. In one embodiment of the invention, portions of a silicon dioxide layer (18) lying adjacent to a conductive interconnect (21) are removed to expose portions of a silicon nitride etch stop layer (16). A dielectric layer (22) having a low dielectric constant is then formed overlying the conductive interconnect (21) and the exposed portions of the silicon nitride etch stop layer (16). A portion of the dielectric layer (22) is then removed to expose the top surface of the conductive interconnect (21) to leave portions of the dielectric layer (22) between adjacent conductive interconnects (21). The resulting interconnect structure has reduced cross-talk between conductive interconnects (21) while avoiding prior art disadvantages of reduced thermal dissipation and increased mechanical stress.

Abstract: In one embodiment, delamination of a patterned silicon nitride anti-reflective layer (26) from an underlying patterned tungsten silicide layer (32), is prevented by forming a thin silicon layer (30) between the patterned tungsten silicide layer (32) and the overlying patterned silicon nitride anti-reflective layer (26).

Abstract: The reliability of integrated circuits fabricated with trench isolation is improved by forming a trench isolation structure with a void-free trench plug (36). In one embodiment, a polysilicon layer (28) is formed within a trench (22) and then subsequently oxidized to form a first dielectric layer (30). The first dielectric layer (30) is then etched and a second dielectric layer (34) is subsequently formed over the etched dielectric layer (32). A portion of the second dielectric layer (34) is then removed using chemical-mechanical polishing to form a void-free trench plug (36) within the trench (22). In addition, reliability is also improved by minimizing subsequent etching of trench plug (36) after it has been formed.

Abstract: A method and apparatus for allowing an integrated circuit to be hard-wired into one of a plurality of modes of operation by providing a plurality of mode bonding pads (104-108). Based upon customer demand, a reset post (102) or like external terminal of the integrated circuit is wire bonded or conductively coupled to only one of the plurality of mode pads (104-108). By bonding only one of the mode pads (104-108) to the reset pin, one of the plurality of distinct modes of operation is enabled upon reset.

Abstract: Power consumption, electromigration, joule heating, and voltage supply ringing are reduced in digital integrated circuits by reducing crowbar current. In one embodiment, crowbar current in a buffer circuit (71) is reduced by electrically connecting the drain region of a PMOS transistor (73), in a first inverter, to a gate electrode (84) of an NMOS transistor (79) and a gate electrode (82) of a PMOS transistor (77), in a second inverter, through a first conductive interconnect (78). In addition, the drain region of the NMOS transistor (75) in the first inverter is electrically connected to the gate electrode (84) of the NMOS transistor (79) and to the gate electrode (82) of the PMOS transistor (77), in the second inverter, through a second conductive interconnect (80). These conductive interconnects allow crowbar current, which is created during a transition between logic states, to be reduced.

Abstract: An apparatus and method for improved wafer bonding by scrubbing, spin drying, aligning, and pressing the polished wafers together. The first wafer (13) is mounted on a flat wafer chuck (11) and a second wafer (14) is mounted on a convex pressure gradient chuck (10). Wafers are scrubbed until a polished contamination free surface is obtained and pressed together. The convex pressure gradient chuck exerts a higher pressure at the center of the wafer than at the periphery of the wafer.