Abstract: A network processor, disposed on an integrated circuit can include an ingress unit having a dual port block random access memory and an egress unit having a dual port block random access memory. The network processor further can include a network interface configured to write packetized data to the ingress unit and read packetized data from the egress unit as well as a coordination processor configured to coordinate movement of data between the network interface, the ingress unit, and the egress unit.
Type:
Grant
Filed:
November 22, 2005
Date of Patent:
September 15, 2009
Assignee:
XILINX, Inc.
Inventors:
Chi Bun Chan, Jonathan B. Ballagh, Nabeel Shirazi