Abstract: A computer-implemented method of performing a Computer-Aided Design (CAD) flow on a circuit design for a programmable logic device (PLD) can include inserting a preprocessing task into the CAD flow prior to a selected task that does not recognize a constraint, wherein the preprocessing task introduces a modification into the circuit design according to the constraint. The circuit design including the modification can be processed through the selected task of the CAD flow. A reversal task can also be inserted into the CAD flow, wherein the reversal task removes the modification introduced into the circuit design by the preprocessing task. The method further can include processing the circuit design through at least one other task of the CAD flow and outputting the processed circuit design.

Abstract: A method of physical circuit design can include the steps of packing components of a circuit design that are dependent upon an architecture of the circuit design and assigning initial locations to each component of the circuit design. The components of the circuit design can be clustered by combining slices and including slices into configurable logic blocks according to design constraints, while leaving enough white space in the configurable logic blocks for post-placement circuit optimizations. The components of the circuit design then can be placed to minimize critical connections. The circuit design can be declustered to perform additional placer optimization tasks on the declustered circuit design.

Abstract: A method of assigning I/O objects to banks of a target device can include concurrently assigning I/O objects, including select I/O objects and clock I/O objects, of the circuit design to I/O groups according to an I/O standard associated with each I/O object. Each I/O group can include only I/O objects of a same I/O standard. The method also can include establishing a plurality of linear constraints for regulating assignment of the I/O groups to banks of the target device. The linear constraints can include range constraints indicating I/O banks capable of hosting clock I/O objects. The method also can include defining mutual relationships among selected ones of the linear constraints. An indication as to whether a feasible solution exists for assignment of the I/O groups to banks of the target device can be provided by minimizing a linear objective function while observing the linear constraints and the mutual relationships.

Abstract: A method of generating timing information for a circuit design can include determining static timing data for the circuit design and identifying a source of timing information for use in functional simulation of the circuit design. The method also can include updating the source of timing information to include at least a portion of the static timing data.

Abstract: Within a high level modeling system (HLMS), a method of visualizing a circuit design can include identifying the circuit design and reading hardware cost information for the circuit design. The method also can include presenting a graphical representation of the circuit design having at least one visual characteristic which can be varied according to the hardware cost information.

Abstract: A method of verifying event handling for a device under test comprised of hardware description language logic within a verification environment can include, for each trigger specified by the verification environment, creating an associated thread within the verification environment. The method also can include defining a time span during which event handling within a device under test is to be performed responsive to each trigger and determining whether event handling for each trigger is performed within the time span associated with that trigger. Event handling for each trigger can be monitored by the thread associated with that trigger. The method further can include indicating triggers that were not handled by the device under test.

Abstract: A method (900) of modeling transactions and performing inertial rejection can include representing a plurality of scalar signals as one or more transaction objects, wherein each transaction object comprises a start index, an end index, values for each constituent scalar signal which correspond to an index within a range specified by the start index and end index inclusive, and a time at which the values are transacted. (400) The method further can include constructing and adding a new transaction object for the plurality of scalar signals (920) and comparing the new transaction object with at least one existing transaction object (925) wherein the at least one existing transaction object occurs earlier in time than the new transaction object and is within a rejection window. At least one of a start index and an end index of the at least one existing transaction object can be manipulated (975).

Abstract: A method of physical design for a programmable logic device can include associating target locations for movable objects with criticality measures and calculating the criticality measure for each target location. A probability for each target location can be calculated. The probability of the target location can be dependent upon the criticality measure for that target location. The method further can include selecting a target location for one of the movable objects for controlled movement during a simulated annealing process. The target location can be selected according to the probability corresponding to each target location.

Abstract: A multithreaded testbench configured to verify a device under test defined by hardware description language logic can include a test case for the testbench executing within a master thread and a generator executing within a sub-thread thread of the master thread. The generator can be configured to create test vectors to be provided to the device under test. The testbench further can include one or more additional modules executing within additional sub-thread(s) of the master thread and a command queue. The additional module(s) can interact with the device under test. The command queue can be configured to store a plurality of commands registered by the master thread. The generator can obtain individual ones of the plurality of commands from the command queue for execution.

Abstract: Within a computer automated tool, a method of physical circuit design can include assigning initial locations to components in the circuit design and determining an initial routing of connections between components in the circuit design using an overlap mode. The method also can include determining timing critical connections and selectively relocating components with at least one timing critical connection prior to performing a detailed routing of the circuit design.

Abstract: A method (400) of placing a circuit design can include the steps of identifying topological levels of a circuit design representation (415) and determining an arrival time for each input signal to a look up table within a circuit design representation (420). The propagation delay associated with each pin of the look up table can be identified (420) such that the input signals of the look up table can be ordered according to the arrival times of each input signal and the propagation delay of each pin of the look up table (435). The method can continue processing each look up table of an identified topological level (440) as well as each topological level of the circuit design representation (455).