Abstract: A union lock for maintaining a union between two conduits is disclosed. In a first embodiment, the union lock includes a pair of bridgepieces. Each of the bridgepieces includes an elongated member. A substantially semicircular flange is coupled to each end of the elongated members. A tab is coupled to each end of the flanges, each tab having a hole formed therein for receiving a connector. During use, the bridgepieces are placed around the conduits and secured to each other by placing the connectors in the holes in the tabs. By tightening the connectors, the elongated members may be compressed against the conduits and against a union nut joining the conduits, thus maintaining the union. In a second embodiment, the union lock includes a pair of elongated members. A substantially circular flange is coupled to each end of the elongated members. A tab is coupled to each end of the flanges, each tab having a hole formed therein for receiving a connector.

Abstract: An LPCVD system is provided in which a mass flow controller is used to control the flow rate of gases passing from a reaction chamber to a vacuum pump. The mass flow controller is disposed within a secondary outlet conduit which connects a first point to a second point of a primary outlet conduit. The primary outlet conduit extends between and in gaseous communication with the reaction chamber and the vacuum pump. The secondary outlet conduit permits gases flowing from the reaction chamber to bypass a primary valve disposed within the outlet conduit downstream of the first point and upstream of the second point. The mass flow controller can advantageously maintain the flow rate of the gases at a setpoint value for a period of time before the flow rate begins to drop. As such, the mass flow controller provides for a reduction in the time required to evacuate the vacuum chamber.

Abstract: A trench isolation structure is provided which includes a dielectric material having a relatively low dielectric constant, K, that is approximately less than 3.8. The capacitance between active areas separated by the trench isolation structure, being directly proportional to K, is thus reduced. As a result, the lateral width of the isolation structure may be decreased without significantly increasing the capacitance between those active areas. In an embodiment, a fabrication process for the trench isolation structure may include a trench is etched within a semiconductor substrate upon which a masking layer is formed. An oxide liner is thermally grown upon the sidewalls and base of the trench. A layer of low K dielectric material is deposited across the oxide liner. A fill oxide is then formed upon the layer of dielectric material. The resulting trench isolation structure includes a low K dielectric material interposed between an oxide liner and a fill oxide.

Abstract: A method is presented for forming a transistor wherein a silicide layer is formed upon an impurity region of a semiconductor substrate. After forming the silicide layer, a gate structure is preferably formed upon an exposed portion of the semiconductor substrate; however, the silicide layer may be formed after forming the gate structure. In order to form the gate structure, a layer of sacrificial material is first formed above the semiconductor substrate. An opening is then patterned through the layer of sacrificial material such that a portion of the semiconductor substrate is exposed. The gate structure preferably includes a metal gate conductor and a metal oxide gate dielectric.

Abstract: A semiconductor topography for a transistor having an ultra-narrow gate conductor. A method for forming the semiconductor topography may include etching a patterning layer extending across a conductive gate layer to form an opening extending to an upper surface of the conductive gate layer. Subsequently, a masking layer is formed upon the exposed upper surface of the conductive gate layer. The patterning layer and portions of the conductive gate layer not shielded by the masking layer are then removed to form a gate conductor. Lightly doped drain impurity areas may then be formed in the semiconductor substrate aligned with sidewall surfaces of the gate conductor. In an embodiment, spacers may be formed adjacent sidewall surfaces of the gate conductor substantially simultaneously with removal of the masking layer and portions of a gate dielectric layer not shielded by the gate conductor.

Abstract: A semiconductor device is provided and formed using self-aligned metal-containing gates within a metal-oxide semiconductor (MOS) process. After forming junction regions within a semiconductor substrate, the gate conductor, or junction implant alignment structure, is at least partially removed to form a trench within a dielectric formed above the substrate. Upper surfaces of the transistor, except the upper surface of the gate conductor, are thereby protected by the dielectric. A metal-containing material can then be arranged within the trench, i.e., in the region removed of the gate conductor. The metal material can be formed either as a single layer or as multiple metal and/or dielectric layers interposed throughout the as-filled trench. The metal-filled trench formation occurs after high temperature cycles often associated with activating the previously implanted junctions or growing gate dielectrics. Thus, low-temperature metals such as copper or copper alloys can be used.

Abstract: The present invention describes the formation of a silicide layer upon a gate conductor by using a masking layer which covers the source/drain regions of the transistor. The method includes forming a masking layer over a semiconductor substrate such that the gate conductor is substantially covered by the masking layer. The masking layer is preferably planarized using any of a variety of well known techniques. After planarization of the masking layer, the masking layer is etched such that an upper surface of the gate conductor is exposed. A silicide layer is preferably formed upon the upper surface of the gate conductor. The masking layer prevents the concurrent formation of silicide upon the source/drain regions.

Abstract: A semiconductor process for forming an interlevel contact. A semiconductor wafer is provided with a semiconductor substrate, a first conductive layer formed on the substrate, and a dielectric layer formed on the conductive layer. A border layer, preferably comprised of polysilicon or silicon nitride is formed on the dielectric layer. Portions of the border layer are then selectively removed to expose an upper surface of a spacer region of the dielectric layer, the selective removal of the border layer resulting in a border layer having an annular sidewall extending upward from the dielectric layer and encircling the spacer region. A spacer structure is then formed on the annular sidewall, preferably, the spacer structure is formed by chemically vapor depositing a spacer material and anisotropically etching the spacer material to just clear in the planar regions with minimum overetch.

Abstract: A process is provided for forming a gate conductor within a trench having opposed sidewalls which approach each other as they pass from the upper surface of a semiconductor substrate to the floor of the trench. According to an embodiment, an opening is formed through a masking layer residing upon the substrate to expose the portion of the substrate to be etched during trench formation. The opening is created using optical lithography and an etch technique. As such, the minimum width of the opening is limited in size. Once the trench has been etched in the substrate, dielectric sidewall spacers may be formed upon the sidewalls of the trench and the lateral boundaries of the masking layer. A gate conductor is subsequently formed between the sidewall spacers. The lateral width of the resulting gate conductor is thus dictated by the distance between the sidewall spacers, and hence by the thickness of the spacer material deposited upon the sidewalls of the trench.

Abstract: A system and method are presented for laundering textiles (e.g., clean room garments) within a clean room facility. The textile laundering system may be used to launder clean room garments. The system includes a washing machine, a dryer, and means for measuring the number and sizes of particulates present within laundered textiles. The washing machine has two opposed sides, a loading side and an unloading side, and at least one portion which allows access to mechanical and/or electrical equipment (i.e., an equipment access portion). The washing machine is positioned within a sealed opening in a vertical partition separating a first laundering area from a second laundering area such that the loading side is located within the first laundering area and the unloading side is located within the second laundering area. The washing machine uses only "ultrapure" water, substantially free of ions, minerals, and organic material, to launder the textiles.

Abstract: A subfield conductive layer is provided, wherein a conductive layer is implanted beneath and laterally adjacent a field dielectric. The subfield conductive layer is placed within the silicon substrate after the field dielectric is formed. The conductive layer represents a buried interconnect which resides between isolated devices. The buried interconnect, however, is formed using high energy ion implant through a field dielectric formed either by LOCOS or shallow trench isolation techniques. The buried interconnect, or conductive layer, resides and electrically connects source and drain regions of two isolated devices.

Abstract: An interlevel dielectric including a tetraethyl orthosilicate (TEOS) oxide and a silicon oxynitride (SiON) etch stop layer is formed for use in integrated circuit fabrication. A SiON layer is deposited onto a semiconductor substrate which may include transistors and/or interconnect levels. The SiON layer is heated before deposition of the TEOS layer. Heating of the SiON layer greatly reduces the number of defects formed during the TEOS deposition. A highly conformal, high-quality interlevel dielectric is thereby formed.

Abstract: A mixed signal integrated circuit is provided having analog and digital circuits coupled to receive respective analog and digital clocking signals. The analog circuit portion may involve switched capacitors which charge and discharge based on timing of the analog clocking signal. The critical sampling moments mandated by the analog clocking signal are purposefully delayed after a quiet time so that pre-existing, digitally induced noise does not impute error in the sampled or loaded voltages. A clocking generator is therefore presented which delays rising edges of the digital clocking signal from falling edges of the analog clocking signal. The amount of delay is chosen to ensure that asynchronously generated noise arising from the digital clocking signal does not substantially affect the critical sampled or loaded voltages. The digital circuit portion can therefore include a memory element having transitory bit lines and a sense amplifier coupled to receive voltages on those bit lines.

Abstract: An integrated circuit fabrication process is provided for incorporating barrier atoms, preferably N atoms, within a gate dielectric/silicon-based substrate interfacial region using gas cluster ion beam implantation. Gas cluster ion beam implantation involves supercooling a gas to form clusters of atoms from the molecules in the gas. Those clusters of atoms are then ionized and accelerated to a target. Upon striking the target, the clusters of atoms break up into individual atoms. The energy of the ionized cluster is uniformly distributed to the individual atoms. As such, the atoms have a relatively low energy, and thus may be implanted to a shallow depth of less than 100 .ANG.. Barrier atoms positioned within a gate dielectric/substrate interfacial region serve to inhibit the diffusion of metal atoms and impurities from an overlying gate conductor into the substrate. Furthermore, the barrier layer provides protection against hot carrier injection into and entrapment within the gate dielectric.

Abstract: A semiconductor process includes forming a spacer support structure on an upper surface of a semiconductor substrate. The semiconductor substrate includes a channel region that is laterally displaced between first and second source/drain regions. A. The spacer support structure includes a substantially vertical sidewall that is laterally aligned over a boundary between the first source/drain region and the channel region of the semiconductor substrate. A gate dielectric is then grown and a transistor gate fabricated by forming a first spacer structure on the sidewall of the spacer support structure. The first spacer structure includes a substantially vertical first sidewall in contact with the spacer support structure sidewall and further includes a second sidewall that is laterally aligned over a boundary between the channel region and the second source/drain region of the semiconductor substrate.

Abstract: The present invention advantageously provides a method for forming a test structure for determining how LDD length of a transistor affects transistor characteristics. In one embodiment, a first polysilicon gate conductor is provided which is laterally spaced from a second polysilicon gate conductor. The gate conductors are each disposed upon a gate oxide lying above a silicon-based substrate. An LDD implant is forwarded into exposed regions of the substrate to form LDD areas within the substrate adjacent to the gate conductors. A first spacer material is then formed upon sidewall surfaces of both gate conductors to a first pre-defined thickness. Source/drain regions are formed exclusively within the substrate a spaced distance from the first gate conductor, the spaced distance being dictated by the first pre-defined thickness. A second spacer material is formed laterally adjacent to the first spacer material to a second pre-defined distance.

Abstract: The present invention advantageously provides a method for determining lithographic misalignment of a conductive element relative to a via. An electrically measured test structure is provided which is designed to have targeted via areas shifted from midlines of corresponding targeted conductor areas. Further, the test structure is designed to have a test pad that electrically communicates with the targeted via areas. Design specifications of the test structure require the midlines of the conductor areas to be offset from the via areas by varying distances. The above-mentioned method involves processing the designed test structure. An electrical signal may then be applied to each of the conductors while it is also being applied to the test pad. The resulting electrical response should be proportional to the distance that a conductor is misaligned from its desired location. Using the electrical responses for all the conductors, it is possible to determine the direction and amount of misalignment.

Abstract: A technique is provided for forming interconnects laterally spaced from each other across a semiconductor topography by a deposited dielectric spacer layer. The lateral distance between each interconnect is advantageously dictated by the thickness of the spacer layer rather than by the minimum feature size of a lithographically patterned masking layer. In an embodiment, a first and second conductive interconnects are formed a spaced distance apart upon a semiconductor topography. The first and second interconnects are defined using optical lithography and an etch technique. A dielectric layer is CVD deposited across the exposed surfaces of the first and second interconnects and of the semiconductor topography. The CVD deposition conditions are controlled so as to form a relatively thin spacers laterally adjacent the sidewalls of the interconnects.

Abstract: A system for the cooling of integrated circuits and, more particularly, for the use of cooling ducts alone or in combination with cooling fans to lower the temperature of integrated circuits. The cooling duct substantially surrounds the integrated circuit. Cooling air may be convectively conducted through the duct to the integrated circuit. Alternatively the cooling air is preferably conducted through the duct to the integrated circuit by at least one cooling fan. Additional cooling fans may be placed within the duct or on the exterior of the duct. The duct may extend through the computer case, communicating with air outside the case. Alternatively, the fans may blow the heated air from the duct outside of the computer case.

Abstract: A method is presented for generating functional tests for a microprocessor having several operating modes and features. A test module template file includes a basic set of instructions required to configure the microprocessor to operate in any one of the several operating modes and with any of the several features enabled. A user modifies a copy of the test module template file to form a test module file which provides a desired operating environment and causes the microprocessor to perform a desired activity and to produce a test result. An assembler takes as input the test module file, along with the contents of any library files to be included, and produces both an assembly code list file and a test code file. The assembly code list file is a computer program listing containing assembly language instructions and data.