Abstract: Fluid transfer controllers (FTCs) having a rotor assembly with multiple rotor blade sets coupled to a hub component of the rotor assembly and further having barrier components forming passages for routing fluid through the multiple rotor blade sets are provided. More specifically, the FTCs include passages for routing fluid along one side of a dividing structure to which a first set of rotor blades is attached and subsequently along the opposite side of the dividing structure to which a second set of rotor blades is attached. The dividing structure may be the hub component of the rotor assembly or a partition separating different levels of rotor blades within the rotor assembly. In some cases, the FTCs may be configured to route fluid from the first rotor blade set to a thermal energy alteration device and further route fluid from the thermal energy alteration device to the second rotor blade set.

Abstract: A transmission system, circuit and method are provided herein for converting differential signals into low duty cycle distortion, single-ended signals that are insensitive to variations in PVT and input common mode voltage. In one embodiment, the signal translation circuit includes an input stage for receiving a pair of differential input signals and producing one or more differential output signals; an intermediate stage for combining the one or more differential output signals into a pair of complementary signals from which a common mode voltage is detected; and an output stage for generating a single-ended output signal that switches from a first value to an opposite value when one of the complementary signals is substantially equal to the common mode voltage.

Abstract: A device for signal transmission between units that are movable along given tracks comprises at least one transmitter for generating electrical signals, at least one conductor arrangement for conducting the electrical signals along a track of movement, and at least one receiver for coupling out electrical signals from a conductor arrangement. At least one conductor arrangement comprises at least one conductor structure for conducting electrical signals, an electric reference surface assigned thereto, and at least one dielectric between the conductor structure and the reference surface. A dielectric of the kind used has a high homogeneity, or a high symmetry with respect to the electrical center of the longitudinal axis of the conductor structure, or both.

Abstract: A memory cell includes a magnetic cell junction having an antiferromagnetic layer within a portion of the cell junction that is adapted to characterize a logic state of a bit written to the junction. More specifically, a memory cell includes, an antiferromagnetic layer arranged in contact with an adjacent magnetic layer within a storing portion of a magnetic cell junction. Such a magnetic cell junction configuration and a method for programming a memory cell with such a cell junction configuration may be used to improve the write selectivity of a memory cell array and reduce the amount of current needed to write a bit to a memory cell. Moreover, a memory cell includes a magnetic cell junction having an aspect ratio less than 1.6. In addition, a memory cell includes at least two resistors.

Abstract: An improved memory cell architecture is provided herein for reducing, or altogether eliminating, chip-level routing congestion in System-on-Chip environments. Though only a few embodiments are provided herein, features common to the described embodiments include: the formation of bitlines in a lower-level metallization layer of the memory array, and the use of word lines and ground supply lines, both formed in inter-level metallization layer(s) of the memory array, for effective shielding of the bitlines against routing signals in the chip-level routing layer.

Abstract: A system and method are disclosed for a Java X font server, capable of displaying high quality text images on a remote display over a network based on the X Window graphical interface. This system and method avoids reliance on the rasterizer in the X server. The Java X font server runs in the client computer and creates the glyphs corresponding to the text to be displayed, using the high performance font rasterizer within the JVM. When the client needs to display text, it makes a request of the X server. If the necessary glyphs are not locally available in the X server, the request is relayed to the Java X font server. The Java X font server then generates the glyphs and transmits them to the X server, where they are cached for subsequent use.

Abstract: A memory array including a conductive line adapted to simultaneously conduct current in at least two distinct directions relative and adjacent to a magnetic junction is provided. In some embodiments, one of the distinct directions may be substantially aligned with an elongated dimension of the magnetic junction, while another of the distinct directions may be substantially aligned with a shortened dimension of the magnetic junction. In yet other embodiments, at least one of the distinct directions may be aligned at an angle between approximately 0 degrees and approximately 90 degrees relative to an elongated dimension of the magnetic junction. In either case, a memory array is provided which includes a contiguous conductive line having a first portion arranged above a magnetic junction of the memory array and a second portion arranged below the magnetic junction. In addition, a method for operating such a magnetic memory array is provided.

Abstract: A dummy structure pattern for fabricating a substantially planar surface within an inactive region of a semiconductor topography is provided. In particular, a semiconductor topography is provided which includes an inactive region comprising a sacrificial annular dummy structure configured to surround an area larger than a square of a minimum critical dimension of a device arranged within an active region of the semiconductor topography. In a preferred embodiment, the area is exclusively designated for a formation of an isolation structure within the semiconductor substrate of the semiconductor topography. As such, a semiconductor topography is provided which includes a separate isolation structure arranged within a spacing of a contiguous isolation structure, which is arranged in a grid pattern within a portion of a semiconductor substrate. Moreover, a semiconductor device is provided which includes an inactive region with a plurality of similarly sized and uniformly arranged annular diffusion regions.

Abstract: In an embodiment of an integrated circuit structure having buried layer substrate isolation and a method for forming same, a buried layer having conductivity type opposite to that of an overlying well region is used for wells containing transistors prone to noise generation, where the wells are of the same conductivity type as the substrate. The buried layer may in some embodiments include a first portion underlying the transistor and a second portion spaced apart from and laterally surrounding the first portion. In some embodiments, the circuit may include a doped annular region of the same conductivity type as the buried layer, where the annular region contacts a portion of the buried layer and laterally surrounds the transistor. The circuit may further include metallization adapted to connect the well and annular region to opposite polarities of a power supply voltage, or in some embodiments to preclude such connection.

Abstract: Several different embodiments of an electronic document delivery system are described including a client machine (e.g., a palmtop/handheld computer or wireless communication device) coupled to a transcoder proxy. The system allows a client machine with limited resources to provide interactive aspects of electronic documents such as Web pages and/or an assistive technology solution for a physically challenged user. The transcoder proxy receives an electronic document including one or more elements and expressed in a first digital format (e.g., HTML or XML). The transcoder proxy assigns a unique identifier to each element, produces an “original” script including at least a portion of the document expressed in a second digital format (e.g., a scripting language), and provides the original script to the client machine. The transcoder proxy may form a model of the document (e.g., a document object model or DOM), and may use the model to produce the original script.

Abstract: A method for reducing the surface roughness of a metal layer is provided. In some embodiments, the method may include depositing a fill layer upon a metal layer and subsequently polishing the fill layer. In some cases, the method may form a surface in which an upper surface of the fill layer is substantially level with at least one of the peaks associated with the surface roughness of the metal layer. In some cases, the surface may include portions of the metal layer and portions of the fill layer residing above the metal layer. In other cases, the method may include forming a surface in which the fill layer is arranged above the metal layer-fill layer interface. In either case, a semiconductor topography having a metal layer with a mean surface roughness less than the mean surface roughness obtained during the deposition of the metal layer may be obtained.

Abstract: Improved semiconductor integrated circuit random access memory (RAM) features pin-compatible replacement of SRAM devices, while providing low power and high density characteristics of DRAM devices. The refresh operations of a DRAM array are hidden so as to faithfully emulate an SRAM-type interface. The new refresh strategy is based on prohibiting the start of a refresh operation during certain periods but otherwise continuously refreshing the array, rather than affirmatively scheduling refresh at certain times as in the prior art. Short refresh operations are initiated frequently, driven by an internal clock that generates periodic refresh requests, except when a read or write operation is actually accessing the memory array. By isolating the DRAM memory array from I/O structures, external memory accesses are essentially interleaved with refresh operations, rather than temporally segregating them as in prior art.

Abstract: A magnetic random access memory (MRAM) device is provided which includes a field-inducing line with a first layer having a plurality of dielectrically spaced conductive segments and a second layer having a conductive portion in contact with at least two of the dielectrically spaced conductive segments. A method for fabricating such a field-inducing layer may include patterning a conductive layer to form the first layer and depositing another conductive layer above at least a portion of the first layer to form the second layer. In some cases, a surface of a first lateral portion of the field-inducing line substantially aligned with a magnetic junction of the device may include a cladding layer, while a surface of a second portion of the field-inducing line substantially aligned with a spacing arranged adjacent to the magnetic junction may be substantially absent of a cladding layer.

Abstract: A system and method are disclosed, according to which, the responsiveness of client/server-based distributed web applications operating in an object-oriented environment may be improved by cofetching read only commands. In an exemplary embodiment, the system and method are implemented by defining special preExecute and postExecute methods of cacheable commands. The preExecute method of a requested command may be invoked to execute secondary commands and then return them to the requesting client. The postExecute method of a requested command may be invoked to place the returned commands in a cache, along with the requested command. In this manner, a single request can be used to execute, retrieve and cache multiple related commands. Cofetched commands are designated by the application developer when the requested command and its associated methods are created, and may be chosen based on their anticipated use in conjunction with the requested command.

Abstract: A system for communication with addressable electronically-controllable appliances using a generalized pointing device is provided. The system includes a pointing device that can communicate with dissimilar types of target appliances from a position remote from those appliances and an appliance interface that makes the target appliances compatible with the pointing device. Use of the system is believed to allow the convenience associated with use of a computer's graphical user interface (GUI) to be realized in communication with physical objects, i.e. the target appliances. In an embodiment for one-way communication from a pointing device to a target appliance, the pointing device may comprise an actuator, an input-output interface, and a transmitter. In an embodiment configured for two-way communication between the pointing device and an appliance, the pointing device may further include a receiver.

Abstract: Several different methods for presenting (e.g., displaying) a hierarchical structure are presented. The hierarchical structure includes multiple elements, and defines hierarchical relationships between the elements. The hierarchical structure may be embodied within an electronic document such as a Web document, an interactive application program, or a map divided into sections. Each element has a “presentation property” which may be a value or a function. A single one of the elements has “focus” (e.g., in accordance with the coding of the document by an author, by default, etc.). A “view depth” method includes forming a model (e.g., a tree structure) of the hierarchical structure. The model includes multiple levels ranked with respect to one another, multiple nodes representing elements, and at least one branch.

Abstract: A microelectromechanical circuit includes a cover attached to a package substrate by a thermoplastic. A MEMS device is disposed between the cover and the packaging substrate. The thermoplastic is substantially free of solvents. In addition, surfaces of the device are substantially free of solvents. The cover, the packaging substrate, and the thermoplastic form a protective enclosure around the device. The MEMS device may be formed on a substrate. The substrate may be attached to the packaging substrate by a thermoplastic. The thermoplastic may also be substantially solvent-free. A method for forming the circuit includes heating a thermoplastic to a temperature sufficient to remove all solvent from the thermoplastic. The temperature may be above a boiling point of the solvent. The method also includes arranging the thermoplastic between the cover and the packaging substrate and applying pressure and heat to the thermoplastic to form a protective enclosure around the device.

Abstract: A system and method are disclosed, according to which, the responsiveness of client/server-based distributed web applications operating in an object-oriented environment may be improved by coordinating execution of cacheable entries among a group of web servers, operably coupled in a network. In an exemplary embodiment, entries are considered to be either commands or Java Server Pages (JSPs), and the system and method are implemented by defining a class of objects (i.e., CacheUnits) to manage the caching of entries. An entry must be executed before it can be stored in a cache. Since this is computationally costly, each cacheable entry has an associated coordinating CacheUnit, which sees to it that only one CacheUnit executes an entry. Once the entry has been executed, a copy of it resides in the cache of the coordinating CacheUnit, from which it can be accessed by other CacheUnits without having to re-execute it.

Abstract: A method for fabricating a bipolar transistor is provided. In some cases, the method may include patterning an epitaxial layer to expose one or more regions of a semiconductor topography. The method may further include depositing an intermediate layer above the exposed regions and remaining portions of the epitaxial layer. A conductive emitter structure may then be formed above and within the intermediate layer. In another embodiment, the method may include etching a first dielectric layer in alignment with a patterned base of a bipolar transistor while simultaneously etching a second dielectric layer in alignment with a patterned emitter structure of the bipolar transistor. In yet other embodiments, the method may include depositing an intermediate layer which is substantially etch resistant to a resist stripping process. In addition or alternatively, the intermediate layer may include etch characteristics that are substantially similar to a conductive layer formed above the intermediate layer.

Abstract: An architecture, system and method are provided for transparently mapping addresses across multiple addressing domains and/or protocols. A destination of a packet can therefore be transferred from a first addressing domain within one network to a second addressing domain within another network, without inserting knowledge into the packet of the relationship between the two separate and independent domains. Transmission modules within one network can be identified with unique identification numbers or addresses assigned during configuration of those modules. The identification numbers assigned internal to the network can be mapped and placed upon the packet as the packet enters the network. Mapping, however, is minimal, knowing that relatively few external devices are connected to select internal devices and/or modules. The packet can then be mapped into the network, where it is then transferred across the network whereupon it is mapped to another network or termination device external to the network.