Abstract: A frequency synthesizer (107) utilizes a variable oscillator (114) the output of which is used as the frequency synthesizer output (115) and is fed to a digital divider (108). The output of the digital divider (108) feeds one input of a phase comparator (109). The other input of the phase comparator (109) is fed from a reference oscillator (116). A phase comparator (109) output controls the variable oscillator (114). The digital divider (108) has a division ratio that is varied with time by a multi accumulator fractional-N division system (112) such that the effective division ratio may be varied by non-integer steps. Due to the time varying division sequence applied to the digital divider (108) there is a residual spurious level on the output signal (115). A second digital sequence from the multiple accumulator fractional. N-division system (112) is generated to reduce this spurious level and is applied to the output of the phase comparator (109).

Abstract: The preferred embodiment of the present invention encompasses an automatic frequency control system implemented in a radiotelephone (101). The radiotelephone (101) includes a frequency synthesizer. The frequency synthesizer uses a division ratio varied with time by a multi accumulator fractional N synthesizer (140) such that the effective division ratio may be varied by non-integer steps. The division ratio is programmed to realize the desired channel frequency, the desired modulation waveform, and any automatic frequency correction offset. An accurate clock is provided to the control logic (104) and the user interface (105) sections of the radiotelephone (101) using a second multiple accumulator fractional N division system (139). This second fractional N division system (139) is programmed based on the automatic frequency control programming of the first fractional N synthesizer (140).

Abstract: The amplifier (201) uses transistors (401,403) such as MOSFET transistors in a current mirror configuration. The transistors (401,403) are easy to package as surface mount devices. The drain port of the first transistor is coupled to an output signal (207) and a bias input signal (VB+). A gate port of the first transistor is coupled to a bias control input (117) and the signal input (115). The source of the first transistor and the source of the second transistor are coupled to an electrical ground (409). A first end of a resistive device (411) is coupled to the gate port and the drain port of the second transistor and a second end of the resistive device (411) is coupled the signal input (115) and the bias control input (117). This amplifier (201) has low sensitivity to the variations of the bias current to the control signal threshold, making the amplifier ideal for use in a radiotelephone (103).

Abstract: A radio receiver directly digitizes the phase of an intermediate frequency (IF) signal with a desired resolution. The frequency of the reference oscillator in the direct phase digitizer is reduced when compared to the frequency previously required for the same resolution. The reduction in the reference oscillator frequency is accomplished by differentiating between IF zero-crossings that occur during the first half of a reference oscillator cycle and zero-crossings which occur during the second half of the reference oscillator cycle. The apparatus utilizes 2 zero-crossing detectors, the first zero-crossing detector is driven by a positive edge of the reference oscillator signal and the second zero-crossing detector is driven by a negative edge of the reference oscillator signal. Depending upon the alignment of the negative edge zero-crossing indicator and the positive edge zero-crossing indicator, the N-bit phase signal is modified or shifted by one-half a phase sector.

Abstract: A radiotelephone system (100) includes a radiotelephone (103) having a subscription lock and a removable subscriber identification module (SIM) card (105) containing an international mobile subscriber identification (IMSI). The subscriber lock is used to restrict registration into the radiotelephone system (100) to only those radiotelephones which contain a SIM card which has an IMSI which falls within a range of valid IMSIs programmed into the radiotelephone or the user has entered a subsidy flag personal identification number (PIN) for permanently disabling the need for a valid IMSI.

Abstract: An Rth-order filter models the frequency response of multiple filters, to provide a filter which offers the control of multiple filters without the complexity of multiple filters. The Rth-order filter can be used as a spectral noise weighting filter or a combination of a short-term predictor filter and a spectral noise weighting filter, referred to as the spectrally noise weighted synthesis filter, depending on which embodiment is employed. In general, the method models the frequency response of L Pth-order filters by a single Rth-order filter, where the order R<L.times.P. Thus, this method increases the control of a speech coder filter without a corresponding increase in the complexity of the speech coder.

Abstract: Transmitting signals containing amplitude modulated (AM) and phase modulation (PM) components requires a transmitter having AM and PM control loops. The PM control loop provides phase modulation, frequency translation and phase predistortion for the transmitter. The phase predistortion/correction is accomplished by using an oscillator, thus, the amount of PA phase correction is essentially unlimited. Additionally, the PM control loop is nested about a power amplifier (PA), allowing the PM control loop to correct for any distortion introduced by the PA.

Abstract: A portable radiotelephone (101) operating in a radio communication system (100), the portable radiotelephone including power consumption controller circuitry (200). The radiotelephone system (100) is designed such that the portable radiotelephone (101) needs to only intermittently receive paging information from a remote transceiver (103) during a control mode. The power consumption controller circuitry (200) utilizes a low cost, low power, low frequency oscillator (237) in conjunction with hardware and software for shutting down a portion of the radiotelephone (101) for a sleep period, when the radiotelephone (101) is not receiving information from the remote transceiver (103). The current sleep period is adapted depending upon the timing accuracy of the previous sleep period.

Abstract: A phase lock loop (PLL) frequency synthesizer is used in a radiotelephone to provide a reference frequency to a transmitter or a receiver. This particular PLL frequency synthesizer has a wide bandwidth control loop having a high current charge pump (417) and a narrow bandwidth control loop having a low current charge pump (411). A deadzone circuit (413) is used at an output of a phase detector (405) to control the application of an error signal to the high current charge pump (417). Additionally, the PLL frequency synthesizer utilizes a loop filter (419). The loop filter (419) receives two correction signals (409', 415') and provides a single control signal for the VCO (voltage controlled oscillator) (423). The loop filter contains two time constants formed from resistive and capacitive elements. The two time constants control the bandwidth of the two control loops.

Abstract: The amplifier uses transistors such as (metal oxide semiconductor field effect transistors) MOSFET transistors in a current mirror configuration. The MOSFET transistors are easy to package as surface mount devices. The output power of the amplifier is controlled by controlling the bias current flowing through the amplifier stage. Additionally, the amplifier has low sensitivity to the variations of the bias current to the control signal threshold. These characteristics make the amplifier ideal for use in a radio transmitter, such as a radiotelephone.

Abstract: The present disclosure includes a discussion of a data transfer system. The data transfer system is responsible for transferring data to and from a radio transceiver (107) and all the corresponding peripheral device ( 111, 113 ) contained in within the radiotelephone (103). The data transfer system includes a data bus (109), a master controller within the transceiver (107) and a peripheral controller within each of the peripheral devices. The data transfer system has an initialization state and a operational state. During the initialization state the data bus (109) operates at a lower frequency than during the operational state. The lower speed increases the time allowed for the assignment of the unique addresses for each of the peripheral controllers. Upon detecting completion of the initialization state, the master controller conducts the change to the operational state.

Abstract: The system includes a battery charger (300) and a battery pack (100). Upon insertion of the battery pack (100) into a retention area (303) of the battery charger (300), a battery pack channel (101) and a corresponding battery charger rail (305) align the battery pack electrical contacts (201) with the electrical contacts (309) of the battery charger. In order to ensure that a reliable electrical connection is made between the two sets of contacts (201, 309), a compliance rib (501) is disposed within the channel (101) of the battery pack (100). The compliance rib (501) creates an interference between the rail (305) and the channel (101), consequently, creating a force against the rail. The interference is calculated to create a sufficient force in combination with the force created by the weight of the battery pack (100) such that the force of the battery pack meets or exceeds the force created by the set of electrical contacts in the battery charger.

Abstract: This patent application discusses a direct phase digitizing apparatus (303) for use in a radiotelephone (101). The direct phase digitizing apparatus (303) accepts a first analog signal (309) having a phase, a voltage range and a first frequency. First, the direct phase digitizer generates an estimated phase map (611) having a second frequency and N-bits of resolution. Second, the direct phase digitizer detects a predetermined-voltage crossing (409) of the first analog signal (309). Third, using the predetermined-voltage crossings, the direct phase digitizer samples the estimated phase map. Fourth, a digital phase signal (623) is generated using the samples of the estimated phase map.