Abstract: A current-type fuzzy processor is disclosed. The fuzzy processor comprises a characteristic decoder for decoding a to-be-identified pattern, a plurality of membership function generators for generating a plurality of membership degrees for the to-be-identified pattern, a weighting decoder for generating a weighting value, a plurality of weighting adjustment circuits for performing weighting operations on the plurality of membership degrees according to the weighting value to generate a plurality of weighted membership degrees, a plurality of accumulators for performing accumulation operations on the plurality of weighted membership degrees to generate a plurality of synthesis membership degrees, a WTA circuit for outputting the plurality of synthesis membership degrees in an order of magnitude; and a timing and control logic for generating timing and control signals for the fuzzy processor.