Abstract: In an approximate content addressable storage system data words are stored in a two dimensional storage array with each data character therein stored in a particularly associated storage row and each data word individually and sequentially character-by-character stored column-by-column. In searching the array for a particular word each storage row associated with a character in the search word is accessed in a manner biased to that character's position in the search word so that the search for all characters occurs effectively in parallel. A searched for character located in its proper position is given maximum value with decreasing value accorded to searched for characters detected one or more positions removed from the proper position in the search word. The value derived for each character is totalled with similar values derived from all other characters in the search word thus arriving at a value indicative of the approximateness of a stored word with the search word.

Abstract: In a data processing system wherein a binary data message is protected by cyclic check codes, synchronization loss tolerance is incorporated by performing a binary transformation after encoding the message but prior to transmitting it or writing it to storage and by performing an inverse binary transformation upon receiving it or reading it from storage but prior to error checking. In one embodiment the transformation involves complementing a plurality of bits. In an alternate embodiment the transformation involves reversing the sequence of a plurality of contiguous bits.

Abstract: In a parallel processing array wherein each processor therein issues a ready signal to signify that it is ready to begin a parallel processing task and initiates the task upon receipt of an initiate signal the parallel processing array is rendered partitionable into parallel processing subarrays by a control node tree having a plurality of control nodes connected to the plurality of processors and in decreasing levels to each other in a tree-like fashion down to a single root node. Each node is controlled to function as a non-root wherein it receives a ready signal from its processor side and passes it along toward the single root node or as a root node whereupon receiving a ready signal it issues back an initiate signal toward the plurality of processors.

Abstract: In a named data processing system, user ownership and verfication of data records is secured by assigning an unique record name to each data record, providing error checking covering both the data record and its associated record name, storing the data record, its associated record name and check code, and requiring the data record name to be provided in order to initiate a fetch operation. Further, the check code enables upon fetching, a verification that an incorrect data record was not inadvertantly fetched due to hardware or other failures. The association of a unique data name with each data record provides for self-descriptive data records thereby permitting the reconstruction of directories which describe the contents of various actual physical locations within an Input/Output system when such directions are lost or otherwise corrupted by hardware or other malfunctions.

Abstract: A high speed modular masking circuit having utility in field extraction, bit checking, and other like operations includes a plurality of input address lines for receiving binary numerical representations, two control lines, and a plurality of output masking lines, the number of output lines being equal in number to two raised in power to the number of input lines. When both control lines are at the same binary logic level, that level is likewise present on all output lines. When otherwise, a number of contiguous ones or zeroes are present on the output lines starting at the first output line, the number of ones or zeroes being equal to the binary numerical representation present at the input address lines and the number being either ones or zeroes depending upon the logic levels present on the control lines. The modular masking circuit is adaptable to various embodiments suitable for SSI, MSI, and LSI.

Abstract: In a large parallel processing environment including a plurality of active registers storing either normalized floating point or integer data a high/low register selection circuit identifies selectively the register or registers storing either the highest or lowest numerical data value. The numerical data in each active register is first converted into a pure binary magnitude pattern having the same relative value as the original numerical data for a select high register search, and the inverse relative value for a select low register search. Thereafter, the binary patterns from all active registers are processed together two bits at a time through an OR network with the OR network output functioning to deactivate all registers having an OR'ed two bit pattern less than the OR network output value. The deactivating process is continued two bits at a time until either only one register remains active or all bits have been processed two bits at a time through the OR network.