Abstract: A system and method for validating adherence of an UII identifier code to one of several prescribed DOD codes by means of a programmed series of tests. First the code is tested for a prescribed header and a last character message. If one or the other is not found, the process stops and an error message is displayed. Field separator characters are identified that divide the message into fields. If the header, end of message character, and field separator are found and tested successfully, the program proceeds, and searches for an identifier of one of the DOD prescribed semantic formats. The semantic format identifier is extracted and tested. If valid, the process proceeds. If not, an error message is displayed. In proceeding, each field is stored, and the data from each field is extracted in accordance with the format identifier that had been extracted.

Abstract: A compensated laser diode transmitter for high speed data transmission is provided with a pair of current switches, a novel current summing circuit and a novel current sink. The power output of the laser is sensed in real data time and employed to generate instantaneous feedback signals capable of instantaneously rebalancing and maintaining the power output of the laser diode.

Abstract: A very rapidly converging adaptive filter which uses a variable scale factor for each weight of the filter. The value of the variable scale factor is chosen for each iteration and is based upon the sign changes of the incremental weight change. The variable scale factor exhibits large values when no sign changes occur and smaller values when sign changes occur. The new filter provides considerable improvement in increase of convergence rate and decrease in residual errors even in the presence of heavy noise while requiring only a modest increase in hardware.

Abstract: An instruction flow control system includes an instruction buffer for receiving stored program instructions. A program address generator signals the instruction buffer for fetching the instructions. A translate RAM decodes the fetched instructions and a translate map gate array generates an address to the translate RAM in response to mapped and remapped instructions being fetched from the instruction buffer. The map gate array looks at an operation code included in the instructions and determines if remapping is required. If so, an address is generated including a constant providing a block of specific addresses and a variable providing a specific address within the block. The mapped instruction includes a seven bit operation code field and, in response to a mapped instruction being fetched, all of the seven bits are mapped directly to the translate RAM address.

Abstract: A coherent detection and decoding circuit coherently recovers data embedded in a self-clocking data signal by recovering the clock in one integrate and dump circuit and recovering the data in a second integrate and dump circuit. The two integrate and dump circuits are connected to the source of self-clocking data signal and to one of the outputs from a clock phase select switch which produces an inphase clock signal and a NOT inphase clock signal. The inphase clock signal is connected to the integrate and dump circuit which produces the output data signal and the NOT inphase clock signal is connected to the clock recovery integrate and dump circuit. When the presence of a data pulse is detected in the clock phase detection circuit the output signal is coupled to the clock phase select switch so as to reverse the output clock signals and synchronize the inphase clock signal with the data embedded in the self-clocking data input signal.

Abstract: A fixture is provided which cleans a plasma etcher of a type that has a holding member with a surface which holds wafers that are to be etched, and an enclosing member which encloses the holding member to form a chamber for the plasma. This fixture operates to produce a large voltage change near the enclosing member and thereby enable the cleaning of the enclosing member by the plasma itself. To achieve such a large voltage change, the fixture is configured to fit inside of the enclosing member, provide a surface which is substantially larger than the surface of the holding member, and make electrical contact with the surface of the holding member. Preferably, the surface provided by the fixture is at least 50% larger than the surface of the holding member.

Abstract: The present invention is concerned with an apparatus and a method of jumping a composite PN code from a current phase position to a desired predetermined phase position so as to enhance acquisition of a composite PN code. The apparatus includes a plurality of individual PN code generators which are connected to a code combiner to produce a composite PN code. Each of the individual PN code generators is driven by its own timing gate for supplying synchronized clock pulses to its own PN code generator. A master clock is connected to a timing gate before being connected to the individual PN code generators. An inhibit input at each of the individual timing gates is provided so that the individual PN generators may be inhibited a predetermined number of clock pulses which causes the PN code generated to be inhibited and has the effect of jumping the PN code a desired number of phase positions.

Abstract: A planar array of radiating elements which includes a plurality of radiating elements which are capable of operating upon electromagnetic signals of different frequency bands in a single planar array.

Abstract: An ultra high frequency multiplexer for combining very high frequency data inputs to produce multiplexed data outputs in the Gigahertz range is provided. Typical ECL output data pulses from integrated circuits are employed as inputs to individual gates of a plurality of dual gates GaAs MESFETS. The second gate of the individual GaAs device is provided with an ultra high frequency clock enable pulse that produces a plurality of pulses are ultra high frequency pulse rates. The outputs of the GaAs devices are delayed one from the other and the delayed outputs are recombined in a combining network to provide a combined multiplexed data output at ultra high frequency.

Abstract: A CMOS buffer receiver is provided for converting TTL or CMOS input voltage signals to CMOS signals so as to drive CMOS loads on VSLI chips. The buffer receiver comprises a reference voltage generator coupled to a compensation network having an output signal which varies with process, temperature and voltage supply. The compensated output signal is coupled to the gates of any number of current source load transistors of a plurality of series connected transistor pairs which comprise individual stabilized input converters all of which have their switchpoint located in the middle of their characteristic curves so that their switchpoints are immune to process, temperature and supply voltage variations.

Abstract: A long phase-locked loop circuit is provided which has an electronic closure circuit in series in the loop. The loop is effectively an open loop until acquisition of the incoming signal at which time the electronic closure circuit closes the phase-locked loop. A novel coincidence circuit is provided which compares the carrier in the loop with a reference frequency and when the two frequencies are equal the coincidence circuit closes the electronic closure circuit.

Abstract: A multi-purpose register formed of various cells of a customized integrated circuit gate array chip having input gate cells, multiplexor cells, flip-flop cells and output gate cells. The flip-flop cells may be segmented into registers of different widths or may be employed as individual flip-flop cells depending upon the mode in which the register array is to be employed.

Abstract: A specialized circuit set is included in a data processing system wherein the circuit set registers can be configured into a serial array. A clock signal distribution system delivers controlled clock signals to selected serial arrays. A maintenance data processor provides predetermined signal groups and addressing apparatus responsive to the predetermined signal groups loads and unloads register arrays in response to the predetermined signals. A predetermined signal group is entered into the serial register array, a predetermined number of clock cycles are applied, and the resulting signals shifted from the serial register array are applied to the maintenance data processor for display or analysis. By comparing the expected result for a given initial state with the actual result of an operation sequence, the accuracy of the operation of the data processing system, or any portion thereof, is thereby determined.

Abstract: In a computer system, there is included a memory unit which includes a volatile memory store, and a memory control circuit connected with the memory unit thereby permitting the computer system to be operated in a step mode, the memory control circuit comprising a step clock generator which generates a gated clock signal. A register element receives a step command signal, an indication from the computer system that the memory unit is to be operated in the step mode, and generates the step mode control signal in response to said step command signal. A shift register receives a strobe command signal from the computer system indicating a request for a memory cycle, and delays the strobe command signal, each stage of the shift register representing a successive step when the computer system is operated in the step mode.

Abstract: In an input/output multiplexer of a data processing unit, a plurality of components, capable of independent activity, provide for the simultaneous execution of a multiplicity of operations involving the exchange of signal groups between a central subsystem and peripheral subsystems. The input/output multiplexer includes apparatus for controlling the receipt from delivery to the central subsystem and peripheral subsystems of signal groups. Apparatus is provided to execute address development normally performed in the central subsystem. Apparatus is also provided to analyze control subsystem signal groups and generate pre-selected command signal groups for delivery to the central subsystem or to the peripheral subsystems. Apparatus in the input/output multiplexer also provides a status of each operation currently in execution.

Abstract: An interface apparatus, which interfaces a communication device to a highway wherein the highway includes a clock line, a data line, and a busy line, comprises a counter element which counts a clock signal transmitted on the clock line to generate a clock value. The counter includes a second input terminal connected to the busy line to disable the counting when a busy signal is present on the busy line. A compare element compares the clock value to a device number value associated with the communication device, each communication device coupled to the highway having a unique device number value, and outputs an enable signal when the clock value and the device number value are equal. A driver element permits data to be transmitted onto the data line in response to the enable signal when the communication device has data to be transmitted.

Abstract: The method by which the right of access to the common communication medium of an initialized local-area network is transferred between modules having access to the medium by the module having such access transmitting a token to a designated existing and properly functioning module. Each such module is assigned a unique address, its MY ADDRESS, and has the data-processing capabilities to determine and store the address of the module to which it last successfully transferred a token, its LAST SUCCESS ADDRESS. Each module also determines the address of a module, if any, between its LAST SUCCESS ADDRESS and its MY ADDRESS, its TRY ADDRESS. The module which has accepted a token will try to pass a token to the module whose address is that of its TRY ADDRESS if its TRY ADDRESS differs from its LAST SUCCESS ADDRESS before attempting to pass a token to the module whose address is that of its LAST SUCCESS ADDRESS.

Abstract: A sense amplifier for a computer memory includes a plural stage differential amplifier. The first stage of the differential amplifier includes an input emitter follower connected to the input of the first stage differential pair. A negative feedback loop is connected around the first stage. The negative feedback loop enhances the response characteristic of the amplifier. Circuit means are also provided which enables the selective steering of energizing current through or away from the second stage of the differential amplifier to provide for the selective blocking of the output of the sense amplifier.

Abstract: In a data processing system having a plurality of CPUs, each CPU is operatively connected to other portions of the data processing system through a system interface unit. The CPU includes a cache memory, an execution unit, and a control unit. Further, each CPU includes an apparatus for verifying the operability of the CPU independent from the operation of the data processing system, which comprises a switch element, interposed between a first port of the CPU and the system interface unit, for decoupling the CPU from said system interface unit in response to a decoupling control signal. A detecting element, detects whether the CPU and the system interface unit are operatively connected to generate a configuration signal indicating the status of the operative connection. A maintenance panel is connected to the switch element and to the detecting element via a second CPU port.

Abstract: The method by which a token-passing local-area network having from two to 2.sup.n modules is initialized, where n is an integer greater than zero. When connected into the network and energized, each module determines if the network is initialized and, if not, which module is to do so. Each module has a unique n bit network address. The module with the smallest network address energized before the network is initialized is identified and begins the process of initialization by transmitting tokens addressed sequentially to network addresses beginning with the next higher address than its own until a token so transmitted is accepted by an addressed module or until a token has been addressed to all network addresses other than that of the initiating module. If after tokens are transmitted to all possible network addresses other than that of the initiating module, the initiating module generates a fault signal to indicate its status.