Abstract: An axial plunger slurry pump comprises a pump body, a sloping cam plate, a swashplate, cylinders, plungers and a pump head. Each of the plungers comprises a plunger body with a rubber piston positioned in its front end and being able to slide over it, and an oil receiving gap communicating with an oil passage disposed between two facing end surfaces of the plunger body and the rubber piston. There are check valves each of which is provided in an oil passage between a ball of each of two-ball links, which ball is coupled with the swashplate, and the swashplate. Each of the cylinder and the plunger body are fitted together by means of a half-and-half locating pad, a cylinder sleeve, a pressing cap, and a locking device. The pump may be used widely in drilling, electric power, mine, building, and metallurgy, etc., for conveying mud, mortar, ore pulp, coal pulp, concrete, etc.
Abstract: In a semiconductor package stack module, an LSI (Large Scale Integrated circuit) is mounted, via fine bumps, on a ceramic carrier substrate or a flexible carrier film on which wiring conductors are formed. After a seal resin has been injected, the chip is thinned by, e.g., grinding. A plurality of such carrier substrates or carrier films are connected to each other by bumps via through holes which are electrically connected to the wiring conductors, thereby completing a tridimensional stack module. The module achieves a miniature, thin, dense, low cost, and reliable structure without resorting to a wire bonding system or a TAB (Tape Automated Bonding) system. In addition, the module has a minimum of wiring length and a desirable electric characteristic.
Abstract: A method of manufacturing a PIN (positive-intrinsic-negative) diode structure includes depositing an insulation or dielectric layer over the bottom PIN diode electrodes, prior to depositing the PIN semiconductor layers. The insulation layer results in a PIN diode structure with reduced leakage current, reduced RIE (reactive ion etching) chamber contamination, the reduction or elimination of post RIE processing, improved yields, and/or expands the potential materials that may be used for the bottom electrode. A corresponding PIN diode structure is also disclosed. The resulting PIN diode structures may be used in, for example, LCD (liquid crystal display) and solid state imager applications.
Abstract: A solid and unitary plastic block which has a textured strip thereon. A self-adhesive transparent tape may be pressed over the textured strip, with air escaping entrapment behind the tape via depressions in the textured strip. Slots on the end of the textured strip provide a termination for the tape ends.
Abstract: A right-angle connector unit used for electrical and removable connection between first and second printed circuit boards (600, 700), which comprises two right-angle connectors (100, 200) of printed circuit boards having base portions to be mounted to the first and the second printed circuit boards, vertical portions, and contacts of conductor patterns extending in parallel with each other between the base portions and the vertical portions and having different lengths, and a cable connector (400) having a flexible flat cable connecting between the vertical portions of the two right-angle connectors in a state where the flexible flat cable is twisted by an angle of 180 degree along a longitudinal direction thereof, the flexible flat cable having conductors which are equal to each other in length.
Type:
Grant
Filed:
February 18, 1999
Date of Patent:
January 9, 2001
Assignee:
Japan Aviation Electronics Industry, Limited
Abstract: A new card connector has a connector element which has, at its opposite ends, projection portions, and a frame element which has a projection guide having a laterally elongated portion in parallel to a card insertion-withdrawal direction at a coupling portion between the frame element and the connector element. When the frame element is coupled with or released from the connector element fixed to a mounting board, an upper side of the laterally elongated portion of the projection guide of the frame element is guided by the projection portion of the connector element so that any contact is prevented between a grounding metal plate of the frame element and pin contacts of the connector element.
Type:
Grant
Filed:
May 14, 1999
Date of Patent:
January 9, 2001
Assignee:
Japan Aviation Electronics Industry, Limited
Inventors:
Takamitsu Wada, Akira Kimura, Manabu Ito
Abstract: In order to provide a ferrule for an optical-fiber connector used for good organization of an optical communication network, the ferrule for an optical-fiber connector is made of a crystallized glass having a composition which consists essentially of, by weight percent, 60-70% of SiO2, 16-25% of Al2O3, 1.5-3% of Li2O, 0.5-2.5% of MgO, 1.3-4.5% of TiO2, 0.5-3% of ZrO2, 2-6.5% of TiO2+ZrO2, 1-5.5% of K2O, 0-7% of ZnO, and 0-3% of BaO. The crystallized glass includes 30-70 volume % precipitation of &bgr;-spodumene solid solution or &bgr;-quartz solid solution having an average grain size not greater than 2 &mgr;m. In addition, the crystallized glass has a bend strength of 200 MPa or more and a thermal expansion coefficient of −10˜50×10−7/° C. at a temperature between −50 and 150° C.
Type:
Grant
Filed:
July 23, 1999
Date of Patent:
January 9, 2001
Assignees:
Nippon Telegraph and Telephone Corporation, NEC Corporation, Nippon Electric Glass Co., Ltd.
Abstract: A multi-colored pixel for a twisted nematic liquid crystal display including red, green, and blue subpixels, wherein each subpixel includes a pair of substrates, a pair of polarizers, opposing electrodes, and a color personalized retardation film which compensates for the different wavelength of each color. The personalized retardation films of the different color subpixels results in elimination of the multi-gap approach and substantially eliminates the problem of different color leakages at different viewing angles, including normal. Also, one polymer based element, preferably a polyimide, functions as both a color filter and a retardation film in certain embodiments of this invention.
Type:
Grant
Filed:
June 24, 1997
Date of Patent:
January 2, 2001
Assignee:
OIS Optical Imaging Systems, Inc.
Inventors:
Adiel Abileah, Gang Xu, Patrick F. Brinkley
Abstract: In a cable connector (1) for connecting a cable (2) having a plurality of core wires (2a,2b), a plurality of support contacts (7) are held by a cover member (3) and extend in a first direction, the core wires are in close contact with the support contacts, respectively, a plurality of base contacts (8) are held by a base member (4) and clamp the core wires over the support contacts, respectively, in a second direction perpendicular to the first direction, the cover member covers the cable and is removably coupled to the base member.
Type:
Grant
Filed:
November 16, 1999
Date of Patent:
December 26, 2000
Assignees:
Japan Aviation Electronics Industry, Limited, NEC Corporation
Inventors:
Koji Higuchi, Osamu Hashiguchi, Hisashi Ishida, Masahiro Yamauchi
Abstract: A manual appliance for cutting tiles, has a carriage (4) which slides above a base (1) which receives a tile to be cut. The carriage (4) has a cutting wheel (19) and a breaking head (23). The breaking head (23) is able to respond to a control means (34), in order to adopt either an idle retracted position so that the wheel comes into contact with and score the tile placed on the base (1), or, a working position in which only the breaking member comes into contact with the top face of the tile. The carriage has a handle (21) for exerting a bearing force on the wheel (19) when it scores the tile, and a bearing force on only breaking member (23) when it is in its working position.
Abstract: A semiconductor integrated circuit device selectively decreasing the parasitic capacitance between wiring lines of a wiring layer is provided. This device is comprised of a semiconductor substructure with a main surface, an insulating layer formed on the main surface of the substructure, a first patterned conductive layer formed on the insulating layer to serve as a first-level wiring layer, and an interlevel dielectric layer formed on the insulating layer to cover the first-level wiring layer. The first-level wiring layer includes a first plurality of wiring lines and a second plurality of wiring lines. The first plurality of wiring lines are located apart from each other at gaps equal to or smaller than a specific value. The second plurality of wiring lines are located apart from each other at gaps larger than the specific value.
Abstract: In a high frequency transmission line having a dielectric substrate and a conductor line which is provided on the dielectric substrate for allowing electric current to flow therethrough, the conductor line has a non-grain-boundary oxide superconductor layer with twin walls but without grain boundaries. The high frequency transmission line is in the form of a plane circuit. It is preferable that an oriented oxide superconductor layer is provided between the dielectric substrate and the non-grain-boundary oxide superconductor layer.
Type:
Grant
Filed:
March 5, 1998
Date of Patent:
December 19, 2000
Assignees:
NEC Corporation, Sumitomo Electric Industries, Ltd., International Superconductivity Technology Center
Abstract: An information processing device functioning as an automated library-data processing device for performing recording/reproducing operations on cartridge magnetic tapes is provided, by which an increase of the device size when providing for an increase of the processed data can be prevented and such increase of the processed data can be simply performed, and the increase in the manufacturing cost of each member can be avoided.
Abstract: In a method for manufacturing a surface channel type P-channel MOS transistor, a gate insulating layer is formed on a semiconductor substrate, and a gate electrode is formed on the gate insulating layer. Then, a P-type impurity diffusion preventing operation is performed upon the gate electrode, and P-type impurities are implanted into the gate electrode.
Abstract: The output signals of the acoustic sensors of the antenna are subjected to a processing of the superdirective kind, with a constraint as regards the modulus and a non-linear constraint which fixes the incoherent noise reduction.The theoretical formulation of these constraints being as follows ##EQU1## the first constraint signifying that the total transfer function is a pure delay .tau., and the second constraint signifying that a limit is fixed for the incoherent noise reduction.The antenna is provided to improve the near-field reception.