Abstract: A branched command/address bus architecture between a memory register and a plurality of memory units includes a main bus connected to the memory register. A first sub-bus is connected to the main bus and branches into a first number of memory unit buses, wherein each of them is connected to a command/address input of a memory unit associated with the same. A second sub-bus is also connected to the main bus and branches into a second number of memory unit buses, wherein each of them is connected to a command/address input of a memory unit associated with the same, wherein the second number is smaller than the first number. Further, the second sub-bus branches into a number of auxiliary buses, wherein the number of auxiliary buses corresponds to the difference between the first number and the second number, wherein each auxiliary bus is capacitively loaded corresponding to the memory unit buses and does not serve for driving a memory unit.