Abstract: Apparatus for limiting the power consumption of a random access memory (RAM), having in combination a counter for counting the number of memory commands in a sample interval, and power governor control logic responsive to the number of memory commands, for limiting the maximum number of transfer requests processed in a sample interval when the counter accumulates a count exceeding a predetermined value.

Abstract: A high-performance contactless electrical energy transmission (CEET) technique which employs the inductive energy transmission principle is described. The proposed technique enables the implementation of high-efficiency, high-power-density, fully-regulated CEET systems suitable for applications with a wide input range and a wide load range. The CEET system in this invention consists of an input-side variable-frequency inverter and an output-side regulated rectifier. A high efficiency of the system is achieved by recovering the energy stored in the leakage inductances of the transformer by incorporating them in the operation of the circuit, and by employing high-frequency-inverter and controlled-rectifier topologies that allow a controlled bi-directional power flow through the transformer. A feed forward, variable-switching-frequency control of the inverter is used to maintain a substantially constant power transfer through the transformer when the input voltage changes.

Abstract: A computer method for compressing, then decompressing an image frame of a specified size, by multiplying the image frame size with a specified color depth coding to obtain an image frame binary code or word, then writing out a mathematical expression that completely describes said image frame binary word or code, whereby said mathematical expression has a one-to-one unique relationship with said image frame binary word or code.

Abstract: A constant frequency, DC/AC inverters that employs a coupled inductor to achieve ZVS in a wide range of load current and input voltage with a reduced circulating energy. In the circuits of the invention, the two windings of the coupled inductors are connected in series and their common terminal is connected to one end of the primary winding of the isolation transformer, which has the other end of the primary winding connected to ground. Each of the other two terminals of the coupled inductors is coupled to the midpoint of the corresponding bridge leg through a series connection of the resonant inductor and a resonant or blocking capacitor. For non-isolated inverter implementations, the common terminal of the coupled inductor is connected directly to the load. The output voltage regulation in the inverters is achieved by a constant-frequency phase shifted control.

Abstract: A method for hydroforming a metallic tube comprising primary hydroforming and secondary hydroforming, wherein in the primary hydroforming step, the metallic tube is formed such that a circumferential length of an expanded portion of the primary-hydroformed tube as measured at a wall center region of the expanded portion becomes substantially equal to or slightly shorter than a circumferential length of an expanded portion of a product as measured at a wall center region of the expanded portion, and in the secondary hydroforming step, movable forming plates incorporated in the dies press the expanded portion formed through primary hydroforming so as to finish the cross-sectional profile of the expanded portion into that of the expanded portion of the product, and said primary hydroforming and secondary hydroforming are continuously performed within the dies. Also disclosed is an apparatus for performing the hydroformation method.

Abstract: A unique data label is affixed to each tracked asset and a unique data label for each location in the enterprise, both real and virtual locations. Location history data of the asset is related to other asset data in a relational data base. Assets typically include system components down to the least repairable/replaceable unit (LRU). The data label, in the preferred embodiment of the invention, is a code label using a code that ensures each label is unique to the asset or location to which it is attached. Here the word location is an inclusive term. It includes the geographical location and the identity of the building in which the asset is housed. Location also includes the identity of the system of which a component is a part and, if relevant, location within the system. It includes also any real or virtual location of interest for subsequent analysis and is ultimately defined by the nature of the system being tracked.

Abstract: A weather monitoring, measuring and reporting system which uses unattended, high-resolution digital cameras and laser rangers to both measure and display weather conditions in a local region, such as the region surrounding an airport. Visibility is estimated by processing images in the camera's field of view at known range distances. The light response of the camera is matched to the light response of the human eye. In a preferred embodiment of the invention, the camera generates a digital pixel image of range objects; that is, prominent terrain objects such as, buildings, water towers, etc. in the camera's field of view. The digital pixel values of these range objects are stored in system memory at known address locations. The contrast between an average background pixel value in a region adjacent to an object and the average object pixel value is used to determine if the object is visible.

Abstract: A state machine computing system provides multiple state registers, a recursive hardware state machine computing system; particularly address translation hardware which can be used in multiprocessors, parallel machines and massively parallel machines. The hardware state machine includes a mechanism to push values into a state register stack and to pop values from the state register stack. The stack consists of a plurality of state registers, one of which is designated the current state register and the remainder designated as prior (or saved) state registers. Recursive logic is provided to increment the current state register. The recursive state machine described provides significant advantages over prior art hardware implementations of guest virtual address translation because guest virtual address translations recursively invoke host virtual address translation.

Abstract: A thermal conductivity measuring device includes a diaphragm portion, a thermal conductivity detector, a temperature sensor, a control section, and a thermal conductivity calculating section. The diaphragm portion is formed on a base. The thermal conductivity detector is formed in the diaphragm portion to perform conduction of heat to/from a sample gas. The temperature sensor is disposed on the base to be near the thermal conductivity detector so as to measure the ambient temperature around the base. The temperature sensor is thermally insulated from the thermal conductivity detector. The control section controls the amount of energy supplied to the thermal conductivity detector such that the temperature difference between the ambient temperature measured by the temperature sensor and the heating temperature of the thermal conductivity detector becomes a constant value.

Abstract: A millicode method for packing the hexadecimal digits from a plurality of bytes in each of two millicode registers (R1,R1) into one of the two millicode registers extracts the rightmost hexadecimal digit from each of a plurality of bytes stored in millicode register R1 and the rightmost hexadecimal digit from each of a plurality of bytes stored in millicode register R2 and stores hexadecimal digits from said extracting step in millicode register R1 with each hexadecimal digit extracted from a byte in register R1 and from a byte in register R2 stored in millicode register R1 in register R1 positions occupied by said plurality of bytes stored in register R1 prior to said extraction step.

Abstract: A. system (i.e. a tool set) provides logic verification at the logic design level in which an external stimulus to the design is derived from a series of generalized timing diagrams that obey the interface protocols of the logic design under test. A timing diagram editor provides a graphical user interface that allows the logic designer to describe his or her logic in a general timing diagram format incorporating permutations of the interface specification. The output of the timing diagram editor is a file that describes the interfaces of the logic; this file can contain multiple timing diagrams that describe different interface interactions. A suitable simulation driver reads the file created by the timing diagram editor, learns the interfaces described therein, and uses simulation randomization algorithms to drive the interfaces with legal scenarios for the interfaces described in the timing diagram.

Abstract: A system for processing a sequence of instructions has a set of compounding rules based on an analysis of existing instructions to separate them into different classes. The analysis determines which instructions qualify, either with instructions in their own class or with instructions in other classes, for parallel execution in a particular hardware configuration. Such compounding rules are used as a standard for pre-processing an instruction stream in order to look for groups of two or more adjacent scalar instructions that can be executed in parallel.

Abstract: In a milli-mode processor, bits (0-6) of an access list entry token (ALET) in the program access register must be zeros in order for access register translation to be successful. When the ALET is being copied from a program access register to a millicode access register, bits 0-3 of ALET, written into the millicode access register, are set to the access register number of the program access register from which the data is being read. This establishes the affinity between the program access register number and any logical fetches which might be attempted by millicode.

Abstract: A data processing system has a processing unit and a memory which provides a common pool of physical storage. This storage is initially assigned as either main storage or expanded storage during power on. Subsequent to the initial assignment, storage assigned as main storage or expanded storage may be unassigned and thus returned to the common pool. Once returned to the common pool, the storage may be reassigned as either main storage or expanded storage. The storage reassignment is done dynamically without requiring a reset action and transparent to the operating system and any active application programs.

Abstract: A certain class of computer has been previously described which has improved performance through the analysis of instructions comprising the computer's control program and appending control information to the instructions in the form of tags. One such computer analyzes instruction cache lines as they are loaded into the cache to create the tags. A disadvantage of that design is the inability to create control information for portions of the cache line whose control tags depend on instructions in another cache line as well as the line being loaded. A method and apparatus is described herein which facilitates creation of control tags based on instructions which reside in different cache lines. The method permits a more complete analysis to be performed, thereby improving processor performance.

Abstract: A pipelined computer processor in a milli-mode architected state tests the validity of a program status word with a mask stored in a millicode general register. The mask indicates bits in the program status word which are to be zeros if the word is valid. A logical AND operation is performed between correspondingly positioned bits in the word and bits in the mask and in addition the status of at least one other bit in the word is checked, a bit other than a correspondingly positioned bit.

Abstract: A massively parallel system has a self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line of the bus is individually phase aligned with the clock signal. Digital data is transmitted at high speeds via the parallel bus to provide a scalable communications network for parallel processing systems while eliminating precise bus length and system clock rates as a critical or limiting factor.

Abstract: A milli-mode routine handles a quiesce interrupt, and causes all the processors in the system to enter a quiesced state. A single bit of a millicode control register indicates a quiesced state and drives an output of the processor to indicate the processor is in a quiesced state. The processor receives a signal indicating all processors in the system are in a quiesced state and latches this value. The output of this latch is sent to the processor instruction unit for use as a millicode branch condition.

Abstract: A millicode instruction loads a millicode address extension register with extended address bits, and an operand access control register that signals when a logical address is to be extended by the extra bits, and when it should be treated as only a 31 bit address.

Abstract: Retry trap in the processor system detects the occurrence of a hardware retry during a millicode routine. In operation, millicode resets the retry trap to "O" at the start of a millicode sequence that is sensitive to a retry operation being at some stage of the millicode sequence. The millicode routine tests the retry latch state at one or more points in the sequence to determine if a retry has occurred since the start of the sequence, which is sensitive to a retry operation. The action taken in response to a determination that a retry operation has occurred depends upon the type of potential damage to the system state as a result of the occurrence of the retry operation during the millicode sequence.