Patents Represented by Attorney, Agent or Law Firm Lawrence D. Cutter, Esq.
  • Patent number: 6700876
    Abstract: Method, system and program storage device are provided for monitoring and ameliorating congestion in a tightly coupled network. Commensurate with sending a packet into the network, a first time stamp is recorded. Upon receipt of an acknowledgment back across the network responsive to sending of the packet, a second time stamp is recorded. The round trip time of the packet is determined and an amount of congestion is estimated using the determined round trip time and a statically predetermined round trip representative of at least one of no network congestion or a known degree of network congestion. The number of flow control tokens for the destination node can be dynamically varied in response to the estimate of the amount of network congestion. If desired, monitoring and estimating of network congestion can be initiated only after identifying the existence of network congestion, for example, represented by a lack of flow control tokens at a sender node for a destination node.
    Type: Grant
    Filed: July 29, 1999
    Date of Patent: March 2, 2004
    Assignee: International Business Machines Corporation
    Inventors: Paul D. DiNicola, Rama Krishna Govindaraju, Mandayam Thondanur Raghunath, Gautam H. Shah
  • Patent number: 6694345
    Abstract: External job scheduling capabilities are provided to a local job control system lacking or having insufficient job scheduling capabilities. This is accomplished by encapsulating running of a user job by the local job control system (LJCS) within running of a marker job at a node management system, which is responsive to an external resource scheduler. The technique includes starting a marker job by the resource scheduler external to the local job control system, wherein the marker job corresponds to a user job to be run by the LJCS; responsive to starting of the marker job, starting the user job by the LJCS; and upon termination of the user job, ending the marker job started by the resource scheduler, wherein starting of the user job by the LJCS is responsive to the resource scheduler's starting of the marker job and wherein ending of the marker job is responsive to termination of the user job.
    Type: Grant
    Filed: October 5, 1999
    Date of Patent: February 17, 2004
    Assignee: International Business Machines Corporatioin
    Inventors: David Paul Brelsford, Joseph Francis Skovira
  • Patent number: 6681225
    Abstract: One or more tables stored in a global data repository are concurrently accessible and modifiable. A client requests the locking of one or more tables within a global server data repository on behalf of a local tree. This locking creates a lock block, which enables at least a portion of the locked tables to be selected, modified and then merged back with the tables residing in the server. One or more other clients may also request to use the same lock block and thus, the same local tree, if shared concurrency is allowed. These other clients would also be allowed to select, modify and merge at least a portion of the tables. The merging of the tables is serialized at the global data repository, if necessary.
    Type: Grant
    Filed: May 31, 2000
    Date of Patent: January 20, 2004
    Assignee: International Business Machines Corporation
    Inventors: Rosario A. Uceda-Sosa, Steven R. Champagne, Kailash N. Marthi
  • Patent number: 6668341
    Abstract: Storage devices are presented which have some facility of error indication and error correction. The basic idea of the present invention is to double only the storing part inside the storing cell and share the environmental logic. Especially in case of multi-port cells this reduces the area penalty significantly because the read/write control within the cell is shared and only placed once. Writing the cell always writes both latches so that they hold the same data. A soft error can flip only one of the two latches. Then, a ‘XOR’ block detects that the data is no longer identical. While the data is read out the check bit indicates that the data is corrupted. The approach of doubling only the storing elements can be extended to implement a triple storing element (10, 12, 30) in the same cell. Then, with the help of a small and simple error correction logic (32) in the cell from a ‘majority vote’ can be seen which bit value is wrong in case of a soft error affecting one bit in the cell.
    Type: Grant
    Filed: October 12, 2000
    Date of Patent: December 23, 2003
    Assignee: International Business Machines Corporation
    Inventors: Ulrich Krauch, Antje Mueller, Juergen Pille, Dieter Wendel
  • Patent number: 6658525
    Abstract: Data is written to an unsegmented buffer located within shared memory. While data is being written to the unsegmented buffer, at least a portion of the data is being read from the buffer. A counter is used to indicate how much space is available in the buffer to receive data. Further, the counter is employed to ensure that the reader does not advance beyond the writer.
    Type: Grant
    Filed: September 28, 2000
    Date of Patent: December 2, 2003
    Assignee: International Business Machines Corporation
    Inventors: Su-Hsuan Huang, William Gole Tuel, Jr.
  • Patent number: 6654780
    Abstract: Managing processor resources in a non-dedicated computer system. An amount of a processor resource is allocated to a real-time application of the computer system. The amount does not exceed a limit chosen for a group of real-time applications, wherein the group includes the real-time application being allocated the resource. A selected amount of the processor resource remains available to execute other types of applications and work on the system. During processing of the real-time application, use of the processor resource does not exceed a chosen maximum value, thereby ensuring the processor resource is not monopolized by the real-time application and allowing other types of work to be processed on the system.
    Type: Grant
    Filed: March 28, 1997
    Date of Patent: November 25, 2003
    Assignee: International Business Machines Corporation
    Inventors: Catherine Krueger Eilert, Peter Bergersen Yocom
  • Patent number: 6625739
    Abstract: To enable a power to the computer to be shut down in a simple configuration and independently of the status of the computer. The power switch 46 is set at the normal position while the computer 10 is operating. Each of the power, reset, and function signals is thus on the high level (A). When the function key 42A is pressed in that status, the function signal can be shifted to a low level signal so as to validate only the key 42A (B). While the power switch 46 is shifted to a pointed position and the key 42A is not pressed, only the power signal is validated, thus a power-on or power-off command can be issued (C). If the power switch 46 is set at a pointed position and the key 42A is pressed, then the level of the reset signal becomes low, thereby the reset signal is validated with the key 42A (D). Consequently, the power to the computer can be shut down forcibly if the power switch 46 is set at a pointed position and the key 42A is pressed, regardless of the status of the computer 10 operation.
    Type: Grant
    Filed: August 22, 2000
    Date of Patent: September 23, 2003
    Assignee: International Business Machines Corporation
    Inventor: Yasuhiro Kobayashi
  • Patent number: 6625638
    Abstract: A logical partition includes at least one dedicated logical processor and at least one shared logical processor. The dedicated processor is a different type of processor than the shared processor, and/or the dedicated processor executes a different dispatching procedure than the shared processor. The use of the shared processor automatically ramps up, as the arrival rate of requests forwarded to the logical partition increases. Furthermore, the use of, the shared processor automatically ramps down, as the arrival rate decreases.
    Type: Grant
    Filed: April 30, 1998
    Date of Patent: September 23, 2003
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey Paul Kubala, John Charles Nagy, Jeffrey Mark Nick, Ira Glenn Siegel
  • Patent number: 6564376
    Abstract: A backing out capability backs out a component of a computing environment, while maintaining the availability of the computing environment. In particular, a component of the computing environment which is associated with at least a portion of a unit of work is backed out from one version to another version. In addition, the backed out component is capable of emulating the other version.
    Type: Grant
    Filed: September 30, 1999
    Date of Patent: May 13, 2003
    Assignee: International Business Machines Corporation
    Inventors: Steven E. Froehlich, Michael K. Coffey, Paul D. Moyer
  • Patent number: 6542929
    Abstract: Dynamic reconfiguration of a quorum group of processors and recovery procedure therefore are provided for a shared nothing distributed computing system. Dynamic reconfiguration proceeds notwithstanding unavailability of at least one processor of the quorum group of processors assuming that a quorum of the remaining processors exists. Recovery processing is implementing by the group of processors so that the at least one processor which was unavailable during the dynamic reconfiguration of the group is able to obtain current state information once becoming active. Each processor of the group of processors includes an incarnation number and a list of member processors which participated in a commit process resulting in its incarnation number. The recovery processing includes exchanging the processors' incarnation numbers and lists of processors for propagation of the current state of the quorum group of processors to the at least one processor now becoming available.
    Type: Grant
    Filed: August 31, 1999
    Date of Patent: April 1, 2003
    Assignee: International Business Machines Corporation
    Inventors: Kenneth C. Briskey, Marcos N. Novaes
  • Patent number: 6542513
    Abstract: A method, system, and associated program code and data structures are provided for a message processing system in which messages are transmitted from source nodes to destination nodes. An “eager” rendezvous transmission mode is disclosed in which early arrival buffering is provided at message destination nodes for a predetermined amount of data for each of a predetermined number of incoming messages. Relying on the presence of the early arrival buffering at a message destination node, a message source node can send a corresponding amount of message data to the destination node along with control information in an initial transmission. Any remaining message data is sent only upon receipt by the source node of an acknowledgement from the destination node indicating that the destination node is prepared to receive any remaining data.
    Type: Grant
    Filed: July 10, 2000
    Date of Patent: April 1, 2003
    Assignee: International Business Machines Corporation
    Inventors: Hubertus Franke, Rama K. Govindaraju, Pratap C. Pattnaik, Mandayam T. Raghunath, Robert M. Straub
  • Patent number: 6519736
    Abstract: Uncorrectable errors are isolated to one component of a computing system comprising a plurality of components. First, upon detection of an uncorrectable error, a special check bit pattern is generated. This check bit pattern is used to indicate the occurrence of an uncorrectable error, as well as the location of the occurrence of the error. Subsequently, the check bit pattern is incorporated into the data word being transmitted, and thus may be used to isolate an uncorrectable error to the exact location of occurrence.
    Type: Grant
    Filed: November 30, 1999
    Date of Patent: February 11, 2003
    Assignee: International Business Machines Corporation
    Inventors: Chin-Long Chen, Mu-Yue Hsiao, Patrick J. Meaney, William Wu Shen
  • Patent number: 6507863
    Abstract: A Dynamic Multicast Routing (DMR) facility is provided for a distributed computing environment having a plurality of networks of computing nodes. The DMR facility automatically creates virtual interfaces between selected computing nodes of the networks to ensure multicast message reachability to all functional computing nodes within the distributed computing environment. The DMR facility employs a group of group leader nodes (GL_group) among which virtual interfaces for multicast messaging are established. Upon failure of one of the group leader nodes, another computing node of the respective network having the failing group leader node is assigned group leader status for re-establishing virtual interfaces. Virtual interfaces are established between the group leader nodes such that redundancy in message routing is avoided.
    Type: Grant
    Filed: January 27, 1999
    Date of Patent: January 14, 2003
    Assignee: International Business Machines Corporation
    Inventor: Marcos N. Novaes
  • Patent number: 6496840
    Abstract: Write requests are performed against one or more resources of a resource group in a persistent and atomic manner. When a write request is received, a backup resource group is updated to reflect data in a current resource group. Thereafter, the write request is performed against the backup resource group. After successfully performing the write operation(s), the backup resource group and the current resource group are swapped in an atomic, consistent manner, such that the backup resource group is now the new current resource group.
    Type: Grant
    Filed: May 31, 2000
    Date of Patent: December 17, 2002
    Assignee: International Business Machines Corporation
    Inventors: Rosario A. Uceda-Sosa, Steven R. Champagne, Kailash N. Marthi, Gregory D. Laib
  • Patent number: 6490693
    Abstract: Dynamic reconfiguration of a quorum group of processors and recovery procedure therefore are provided for a shared nothing distributed computing system. Dynamic reconfiguration proceeds notwithstanding unavailability of at least one processor of the quorum group of processors assuming that a quorum of the remaining processors exists. Recovery processing is implementing by the group of processors so that the at least one processor which was unavailable during the dynamic reconfiguration of the group is able to obtain current state information once becoming active. Each processor of the group of processors includes an incarnation number and a list of member processors which participated in a commit process resulting in its incarnation number. The recovery processing includes exchanging the processors' incarnation numbers and lists of processors for propagation of the current state of the quorum group of processors to the at least one processor now becoming available.
    Type: Grant
    Filed: August 31, 1999
    Date of Patent: December 3, 2002
    Assignee: International Business Machines Corporation
    Inventors: Kenneth C. Briskey, Marcos N. Novaes
  • Patent number: 6480897
    Abstract: A program product for a message processing system in which messages are transmitted from source nodes to destination nodes. A transmission flow control technique is disclosed in which the source node optimistically sends control information and a data portion of a message, and wherein a destination node discards the data portion of the message if it is unable to accommodate it. The destination node, however, retains enough of the control information to identify the message to the source node, and when the destination node is subsequently able to accommodate the data portion, the destination node issues a request to the source node to retransmit the data portion of the message. Discarding of one message is followed by discards of sequential messages, until the destination node is able to accommodate the data portions of messages.
    Type: Grant
    Filed: December 29, 1997
    Date of Patent: November 12, 2002
    Assignee: International Business Machines Corporation
    Inventors: Christine M. Desnoyers, Douglas J. Joseph, Francis A. Kampf, Alan F. Benner
  • Patent number: 6464530
    Abstract: A strain relief for a plurality of cables comprises two portions which act together to clamp the cables in position without the use of tools in a manner which is intuitive to a user. The first portion has hook elements projecting from a surface, each hook element being for retention of a cable. A second set of hook elements is also provided. A second portion has a cable receiving opening corresponding to the cable receiving opening in the first portion. The second portion latches to the first portion, so as to clamp the cables.
    Type: Grant
    Filed: October 30, 2000
    Date of Patent: October 15, 2002
    Assignee: International Business Machines Corporation
    Inventors: Peter Andrew Smith, Ian McFarlane Denny, Joseph James Hall
  • Patent number: 6463563
    Abstract: An error correction code for single symbol error correction and double symbol error detection is generated according to a novel modular H-matrix. The H-matrix utilizes a modular design with multiple iterations of a plurality of subsets. In particular, one example of this H-matrix includes a plurality of rows and columns with each of at least one row of the H-matrix comprising, in part, multiple iterations of one subset of the plurality of subsets. The remainder of the rows, comprises, in part, a cyclic permutation of all of the remaining subsets of the plurality of subsets.
    Type: Grant
    Filed: November 30, 1999
    Date of Patent: October 8, 2002
    Assignee: International Business Machines Corporation
    Inventors: Chin-Long Chen, Mu-Yue Hsiao, Patrick J. Meaney, William Wu Shen
  • Patent number: 6462694
    Abstract: A priority encoding technique is provided which outputs a code corresponding to the highest-priority input line among input lines having a true value when true values are input to more than one of the input lines, which are prioritized and given codes. The technique includes performing higher-order-bit encoding by outputting higher-order bits corresponding to the group having its highest priority among those groups distinguished by the higher-order bits to which true values are input; and performing lower-order-bit encoding to output lower-order bits corresponding to the input line having the highest priority among input lines to which the true values are input. Further, the lower-order-bit encoding includes invalidating the input of true values into the input lines to groups having lower priorities than the highest-priority group distinguished by the higher-order bits.
    Type: Grant
    Filed: October 23, 2000
    Date of Patent: October 8, 2002
    Assignee: International Business Machines Corporation
    Inventor: Hisatada Miyatake
  • Patent number: 6460157
    Abstract: Data is protected during conversion from one or more source error correction codes to one or more destination error correction codes by generating check bits of the destination error correction codes prior to a detection for errors in the source error correction codes. After commencing generation of these check bits, a detection is made for any errors in the source error correction codes. These errors are subsequently corrected in the destination error correction codes by complementing the erroneous bits of the destination error correction code. In addition, various logic reduction techniques may also be implemented to increase efficiency.
    Type: Grant
    Filed: November 30, 1999
    Date of Patent: October 1, 2002
    Assignee: International Business Machines Corporation
    Inventors: Chin-Long Chen, Mu-Yue Hsiao, Patrick J. Meaney, William Wu Shen