Abstract: A virtual stack structure utilizing Write Pointers and Read Pointers for providing pipelined data words on a first-in first-out basis to a memory structure is described. The virtual stack structure incorporates a plurality of Stack Registers each having an unique Write Tag and Read Tag associated therewith. The Write Tags are utilized to through-check the decoding of the Write Pointer and to issue Write Tag Error signals when it is determined that the Write Pointer has been improperly decoded. Circuitry is provided for checking the appropriate loading of the Write Pointer in the stack, and issuing an error signal when improper loading is sensed. Each of the Stack Registers has an unique Read Tag associated therewith that is utilized to through-check the decoding of the Read Pointer and to issue Read Tag Error signals when improper decoding is detected.

Abstract: A selective, non-manual power controller provides the selective, non-manual power control of various components of a data processing equipment from and reports the power status of such components to a central location. As opposed to pass power controllers which were limited to powering on or off all of the computer equipment controlled by a given controlling element, this invention provides a non-manual capability for remotely powering on or off any one or more components of a system or systems in a selective manner and providing the power status thereof. By being able to selectively activate or deactivate any or all of the components of a data processing system, the ability to conserve electrical energy is optimized. In many cases, a single component or a set of components are not used for extended periods of time, such as an entire production period or at least a large portion of a production period.

Abstract: A series of instructions N, N+1, N+2, etc. are issued by an instruction buffer 14 at a fixed clock rate in a pipelined method to parallel instruction flow path 6 and control word flow path 8, each path including a serial coupled holding register 20, 21, an instruction register 18, 19 and a function register 16, 17. If instruction N is a jump instruction, it and the related control word, when stored in the function registers 16, 17 causes the jump target instruction and the related control word of the jump instruction N to be entered into the holding register 20, 21. If the jump instruction N jump conditions are satisfied, the jump target instruction and related control word are written into the instruction registers 18, 19 and then into the function registers 16, 17 to be executed by the associated system.

Abstract: The preferred embodiment shown involves forming the memory system of B memory banks, where B is preferably a prime number, but may be a nonbinary number, i.e., B=2.sup.X, where X is a positive integer, and where the requested address=(Q+R)B. The address translation system for each requestor seeking access to the memory system includes a ROM and an adder. The ROM is comprised of two ROMs, Q ROMa and Q ROMb. ROMb stores in successive memory locations a first portion Qb of the memory system address and Q ROMa stores in successive memory locatins a second portion Qa of the memory system address. An adder sums the data, Qa+Qb, stored in the addressed memory locations of Q ROMa and Q ROMb while Q ROMa stores in successive memory locations a Bank R portion that specifies the one of the B banks in which the sum Qa+Qb addresses the selected memory address in the selected memory bank of the memory system.

Abstract: A Multiple Unit Adapter is disclosed which provides a high speed interface between a single Scientific Processor and a plurality of High Performance Storage Units. This Multiple Unit Adapter is required only when more than one High Performance Storage Unit is used in the data processing system. Since the Scientific Processor of the data processing system is configured with only a single High Performance Storage Unit port its design is simplified and, of course, its cost is reduced. This is especially so when the data processing system uses only a single High Performance Storage Unit. It therefore enables the data processing system to be expanded into a system having a larger memory capacity while keeping the design of the Scientific Processor constant, less complex and consequently less costly.

Abstract: A local store for a scientific vector processor which provides high speed access to scalar variables, parameters, temporary operands, and register save area contents of the system. Basically, the local store is a general purpose storage structure which provides access which is as fast as access to the general or vector registers of the vector processor. It is capable of being accessed either directly or indirectly via indexing. It resides in the virtual address area of the machine so that it is accessible for either reading or writing by the host programs. Because of its positioning in relation to the high performance main storage unit its size is transparent to the other programs of the system since it overflows automatically into the main storage unit. It also has multiple interfaces which provide a more simple matching of the bank widths and transfer rates of the rest of the scientific processor.

Abstract: An improved partially duplicated stack structure for ensuring data integrity through a pipelined stack is described. An improved virtual first-in first-out stack structure having a plurality of parallel stacks, each for storing predetermined segments of data signals from a total data word is described in conjunction with one or more associated compare stack structures which are commonly accessed during loading and reading the stack. The compare stack is arranged for storing predetermined selected bit groupings associated with each of the segments of data signals. The bit groupings from the compare stack are compared with like-situated bit groupings from the associated segments of data signals at readout. Failure of the bit-by-bit comparison results in an indication that a stack address decode error has occurred, thereby providing through-checking of the integrity of the functioning of the stack structures.

Abstract: A method and a means of increasing the performance of an instruction buffer in a digital data processing system is disclosed. The improvement is accomplished by by-passing the content addressable memory operation which has heretofore been utilized to access page addresses in the instruction buffer. As each word included on the same page was accessed, the CAM was repetitiously activated even though it was accessing the same page. In the present system, word accesses made to the same page are handled in a much improved manner. In the present system, a comparator is implemented in the system which compares the presently reference page with the previously referenced word, so that when a match is noted, i.e., the same page is indicated, the CAM is bypassed and successive requests made to the same page are satisfied from the instruction buffer by a validity designator which designates that the presently referenced word is the correct one.

Abstract: A high performance pipelined virtual first-in first-out stack structure having a data stack portion and a split control stack portion is described. The stack structure is intended for use in a pipelined high performance storage unit that can pipeline up to R input requests without having received an acknowledge that a request has been honored. The data stack incorporates R+1 data stack registers to provide over-write protection to ensure that at least R data stack registers are protected from over-write. The split control stack utilizes even address and odd address stack registers. Memory bank request signals are stored sequentially and alternately between the even address and odd address stack registers.

Abstract: Within a High Performance Storage Unit (HPSU) digital memory resource, plural ones (up to 4) of a multiplicity (nominally 8) of independently operative storage memory banks, each consisting of four storage modules, are each simultaneously communicating voluminous read data (nominally 144 data bits plus 16 parity bits) read from each to a respective one of plural (nominally 4) output ports of the memory resource, said communicating being upon and via a selected one of a like plural number (4) of wired-OR communication buses.

Abstract: An improved multiple port memory system has a priority network for selecting between multiple units seeking access thereto. The priority network responds to requests for access and provides encoded port identifying signals indicative of the port to have access. Decode circuitry decodes the encoded port identifying signals and provides unique port enabling signals for the selected port. Decode error detection circuitry responds to the decoded port enabling signals and provides a decode error indication any time multiple port enabling signals are detected as occurring simultaneously. Port Code error detecting circuitry respond to the encoded port identifying signals and the decoded port enabling signals to provide a code error indicating signal when a port code error condition is detected.

Abstract: In an n-wide (n nominally equals 4) snapshot priority network apparatus the access of n+1 requestors to a memory unit is prioritized. Two requestors--the lowest priority one of normal system requestors called instruction processors plus a maintenance exerciser type requestor--share a single memory port which is nominally the lowest priority one of n such prioritized ports. Requests from both requestors are both honored upon a single priority snap, the instruction processor request nominally proceeding before the maintenance processor request. Although the n-wide priority network remains generally faster than any (n+1)-wide priority network, the maintenance exerciser type requestor is expediently serviced and cannot be locked out of access to memory by the competing higher priority requests of the instruction processor.

Abstract: A method and apparatus for performing high speed graphics fill is provided. Any closed line geometric shape or polygon that can be defined by pixel position is stored in memory. The memory pixel positions are stored in address locations corresponding to row and column positions. A first sequential examination of the data is made in reverse raster scan order to make a preliminary determination of the pixel positions inside the closed polygon. A second sequential examination of the data is made in forward or regular raster scan order and a final determination is made whether the pixel positions are inside the polygon and shall be filled. The final determination of pixel positions to be filled is stored shortly before the graphics fill operation is performed so that the fill operation is performed in raster scan time at high speed.

Abstract: The invention relates to a test unit for testing the operation and accuracy of a microcomputer controlled aircraft fuel gaging system or processor which involves a characterized liquid gaging system sensor and sensor apparatus for determining a depth of liquid in a tank at a particular location in the tank. The fuel gaging system sensor is the wetted length type capacitance probe. The test unit hereof performs tests on processors prior to their being installed in aircraft and operates to provide a real time simulation of capacitive probes which in effect replaces the aircraft tank and probes thereof in testing the processors. A single reference capacitor simulates by multiplexing the capacitances of the set of tank probes, which in operation are scanned in succession by the processor, to verify the proper operation of the processor.

Abstract: A temperature sensor uses a thin film structure having an RF sputtered layer of a temperature sensitive material forming a thermistor element deposited on an electrically insulating and thermally insulating substrate. The sensor may include a plurality of deposited thermistor layers arranged on both sides of the substrate and having electrical connection means attached thereto. The sensor is arranged on a substrate suitable for inclusion in a detector cell forming a chamber arranged to be connected to a source of fluid flow.