Abstract: The present invention is a persulfate etchant composition especially useful for dissolving copper during fabrication of microelectronic packages. The etchant is characterized by its ability to selectively etch copper in the presence of nickel, nickel-phosphorous and noble metal alloys therefrom. Furthermore, no deleterious galvanic etching occurs in this etchant-substrate system so that substantially no undercutting of the copper occurs. The combination of high selectivity and no undercutting allows for a simplification of the microelectronic fabrication process and significant improvements in the design features of the microelectronic package, in particular higher density circuits. The persulfate etchant composition is stabilized with acid and phosphate salts to provide a process that is stable, fast acting, environmentally acceptable, has high capacity, and can be performed at room temperature. A preferred etchant composition is 230 gm/liter sodium persulfate, 3 volume % phosphoric acid and 0.

Abstract: An electronic structure. The electronic structure comprises a layer. The layer includes: a cylindrical volume; a fully cured annular volume of a photoimageable dielectric (PID) material circumscribing the cylindrical volume; and a partially cured remaining volume of the PID material circumscribing the annular volume. The cylindrical volume may include a via. The structure can include a power plane.

Abstract: A cavity-type chip module. The module is formed with an adhesive joining layer of photoimageable material interposed between a metal stiffener and a laminate top layer with a central aperture defined in the top layer. The photoimageable material is exposed to actinic radiation, except for an area corresponding to the aperture in the top layer. The unexposed area of photoimageable material is developed away to form a window in the joining layer. The top layer, joining layer, and stiffener are laminated together with the window and aperture aligned, and with a portion of the stiffener spanning the aperture to define a cavity in the resulting substrate. The removal of the unexposed photoimageable material, and the selective exposure of the joining layer to actinic radiation, keep the cavity free of photoimageable material and inhibit bleeding of the photoimageable material into the cavity from its inner edge.

Abstract: An electronic structure that includes a copper-Invar-copper (CIC) laminate of negligible thickness, such as a thickness not exceeding about 0.5 microns. The electronic structure may have a via passes through the CIC laminate such that the via is plated with a ring of copper. The ring of copper and the copper in the CIC laminate may have about the same grain structure.

Abstract: A semiconductor chip carrier assembly which includes a flexible substrate having a metallicized path on one of its surfaces in electrical communication with a semiconductor chip. A stiffener is disposed adjacent to said flexible substrate and is bonded thereto by an adhesive composition. The adhesive composition which comprises a microporous film laden with a curable adhesive is disposed between the flexible substrate and the stiffener. A cover plate is adhesively bonded to the semiconductor chip and to the stiffener. A process of making the assembly involving disposition of the flexible substrate in a vacuum fixture upon which the adhesive composition and stiffener is placed followed by the application of heat and pressure to cure the curable adhesive is also described.

Abstract: Electrical nets are prepared by bonding an electrically conductive element in a deleted plated via. The electrically conductive element has a headed portion that contacts the bottom of the laminate and the other end of the electrically conductive element electrically connects to a BGA pad or surface trace line.

Abstract: A multilayered laminate, substructures and associated methods of fabrication are presented. The multilayered laminate includes in sequential order: (a) a first intermediate layer having microvias and conductive lands; (b) a plurality of signal/power plane substructures, wherein a dielectric material of an intervening dielectric layer insulatively separates each pair of successive signal/power plane substructures and (c) a second intermediate layer having microvias and conductive lands.

Abstract: A multilayer CTE compensated chip interposer for connecting a semiconductor chip to a laminate chip carrier. A first dielectric layer, on the chip side of the interposer, is made of a stiff, high elastic modulus, material, such as a ceramic material, with a CTE closely matching the CTE of the chip. A second dielectric layer, on the laminate chip carrier side of the interposer, is made of resilient, low elastic modulus, material with metallurgy formed thereon, such as circuit board material, with a composite CTE closely matching the CTE of said chip carrier. A third dielectric intermediate layer, laminated between said first and second layers, is made of a low elastic modulus material with metallurgy formed thereon, such as a Teflon/glass particle material, with a composite CTE between the CTEs of said first and second layers.

Abstract: The present invention relates to a method and tooling for forming a stent and the stent so formed. The stent includes filaments of a first material and joints of a second material. The present invention also discloses the above described stent in combination with an angioplasty balloon. The tooling in accordance with the present invention provides a fixture having grooves that receive the filaments of the stent to hold the filaments in place for joining. The joining of all of the filaments can be performed simultaneously by laser welding or injection molding a joint material. The tooling in accordance with the present invention also provides the capability to mold the stent as one piece. The method in accordance with the present invention includes the steps of providing a fixture with internal grooves, placing filaments into the grooves and joining the filaments together.

Abstract: Plastic ball grid array (PBGA) packages comprised of organic carriers on which are mounted and encapsulated semiconductor chips, providing for the mounting of so-called flip-chips. The chips are overlaid with a heat spreading thermally-conductive cap of a mesh-like material which is interstitially filled with an adhesive to prevent delamination caused by mismatches in the coefficients of thermal expansion, which result in contractions which cause the entire package arrangement to warp, leading to delamination between an encapsulant and cap and resulting in failure of connect joints and the ball grid arrays.

Abstract: Semiconductor chip structures are provided with embedded thermal conductors for removing heat from one or more electrically conductive circuit members thereof, wherein the circuit members are formed on one or more dielectric layers above a substrate, each layer having a low dielectric constant and a low thermal conductivity. One or more cooling posts, for example, multiple thermally conductive plugs, are selectively disposed within the semiconductor chip structure adjacent to one or more electrically conductive members and thermally coupled thereto so that heat produced by the members is transferred into and through the cooling posts for forwarding to the substrate and/or to an upper surface of the semiconductor chip structure. The backside of the substrate has a thermal sink thermally coupled thereto and electrically isolated from the substrate.

Abstract: A tamper resistant enclosure for protecting an electronic device containing sensitive information (e.g. an electronic cryptographic card), is provided. The enclosure includes an external cover and an internal cover. Four screws (one at each corner) secure the internal cover to the device and the external cover by means of standoffs. A washer is interposed between the device and the standoff. The device has a dielectric substrate with a metal pad around each hole for ensuring the electrical connection to ground through the washer, the standoff and the conductive body of the external cover. When one of the screws is at least partially removed and the internal cover is moved, the circuit is interrupted and the system assumes that a tampering is being attempted. The circuit is designed to give an alarm and/or destroy all the sensitive information contained in the protected electronic device.

Abstract: A heat sink for a transceiver optoelectronic module including dual direct heat paths and structure which encloses a number of chips having a central web which electrically isolates transmitter and receiver chips from each other. A retainer for an optical coupler having a port into which epoxy is poured. An overmolded base for an optoelectronic module having epoxy flow controller members built thereon. Assembly methods for an optoelectronic module including gap setting and variation of a TAB bonding process.

Abstract: The present invention relates to a structure for providing an interconnect between layers of a multilayer circuit board. The structure comprises a stack that includes at least one layer and a via opening that extends through at least one layer of the stack. Each individual via opening is filled with a solid conductive plug and each solid conductive plug has a first contact pad and a second contact pad.

Abstract: An integrated circuit chip carrier assembly is provided by joining a substrate having electrically conductive regions on at least one major surface thereof to a stiffener by a bonding film. The bonding film comprises a dielectric substrate having a thermoset adhesive on both of its major surfaces. The thermoset adhesive prior to the bonding is a B-stage adhesive, is tack-free at normal room temperatures and is solvent free.

Abstract: A method and apparatus for desoldering electronic components from a substrate. A vacuum is used to enhance the flow of a hot gas under an electronic component to reflow the solder connections attaching the electronic component to a substrate. Water vapor is added to the hot gas to increase the heat capacity of the hot gas. A system for periodically changing the direction of flow of the hot gas and vacuum under the electronic component is used to uniformly heat the solder connections. A method and apparatus for depositing underfill material between an electronic component and the substrate on which the electronic component is mounted. A vacuum is applied to enhance the flow of underfill material into the space between the electronic component and the substrate.

Abstract: A surface metal balancing structure for a chip carrier, and an associated method of fabrication, to reduce or eliminate thermally induced chip carrier flexing. A substrate, such as a chip carrier made of organic dielectric material, is formed and includes: internal circuitization layers, a plated through hole, and outer layers comprised of an allylated polyphenylene ether. A stiffener ring for mechanically stabilizing the substrate is bonded to an outer portion, such as an outer perimeter portion, of the top surface of the substrate, in light of the soft and conformal organic material of the substrate. The top and bottom surfaces of the substrate have metal structures, such as copper pads and copper circuitization, wherein a surface area (A) multiplied by a coefficient of thermal expansion (C) is greater for the metal structure at the bottom surface than for the metal structure at the top surface.

Abstract: A structure and method for providing an antifuse which is closed by laser energy with an electrostatic assist. Two or more metal segments are formed over a semiconductor structure with an air gap or a porous dielectric between the metal segments. Pulsed laser energy is applied to one or more of the metal segments while a voltage potential is applied between the metal segments to create an electrostatic field. The pulsed laser energy softens the metal segment, and the electrostatic field causes the metal segments to move into contact with each other. The electrostatic field reduces the amount of laser energy which must be applied to the semiconductor structure to close the antifuse.

Abstract: A method and structure for implementing dense wiring, in printed circuit board or chip carrier applications, which provides superior electrical characteristics while preserving the system resistance and characteristic impedance requirements. The dense wiring is characterized by requiring that all wires have a sufficient cross-sectional area to ensure the longest wires used do not exceed a maximum resistance by either sorting wire lengths and allowing acceptably “short” wires to use denser circuit lines or by providing short lengths of short circuit lines in those areas where necessary and switching to less dense, lower resistance lines where possible. The disclosure also provides for dense wiring in component areas that can then be converted to low resistance wiring with application of a buried via.

Abstract: A structure and methods for reinforcing a semiconductor device to prevent cracking is provided. The device may take the form of a semiconductor chip or a semiconductor chip package. When a semiconductor chip is provided, an adhesion layer is applied over its top surface, followed by the application of a reinforcing layer over the adhesion layer. When a semiconductor chip package is provided, the package first undergoes a cleaning process, followed by the application of an adhesion layer over its top surface and, lastly, the application of a reinforcing layer over the adhesion layer.