Patents Represented by Attorney Lee E. Chastai

Find this attorney in the Justia Lawyer Directory

  • Memory cache with low power consumption and method of operation
    Patent number: 5550774
    Abstract: A memory cache (46) has a plurality of tag arrays (20, 22, 24, 26), a plurality of comparators (38, 40, 42, 44), a plurality a data arrays (12, 14, 16, 18), and a plurality of sense amplifiers (48, 50, 52, 54). The memory cache executes a parallel tag and data array access but does not enable any sense amplifier until a comparator indicates a cache hit. Consequently, the memory cache is suitable for use where power consumption and speed are equally important design constraints.
    Type: Grant
    Filed: September 5, 1995
    Date of Patent: August 27, 1996
    Assignee: Motorola, Inc.
    Inventors: Michael L. Brauer, Paul A. Reed, John L. Duncan