Patents Represented by Attorney Leffert Jay & Polglaze, P.A.

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  • Adjusting for charge loss in a memory
    Patent number: 8174887
    Abstract: Memory and methods of operating a memory adjusting an output voltage of an analog storage device, such as a data cache capacitor holding a voltage level representative of data, in response to an estimated charge loss are useful for compensating for the effects of charge leakage from the analog storage devices.
    Type: Grant
    Filed: April 20, 2010
    Date of Patent: May 8, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Frankie F. Roohparvar
  • Floating-gate structure with dielectric component
    Patent number: 8174061
    Abstract: Floating-gate memory cells having a floating gate with a conductive portion and a dielectric portion facilitate increased levels of charge trapping sites within the floating gate. The conductive portion includes a continuous component providing bulk conductivity to the floating gate. The dielectric portion is discontinuous within the conductive portion and may include islands of dielectric material and/or one or more contiguous layers of dielectric material having discontinuities.
    Type: Grant
    Filed: February 3, 2009
    Date of Patent: May 8, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Chandra Mouli, Gurtej S. Sandhu
  • Independent well bias management in a memory device
    Patent number: 8174893
    Abstract: Methods for programming a memory device, memory devices configured to perform the disclosed programming methods, and memory systems having a memory device configured to perform the disclosed programming methods, for example, are provided. According to at least one such method, multiple independent semiconductor well regions each having strings of memory cells are independently biased during a programming operation performed on a memory device. Reduced charge leakage may be realized during a programming operation in response to independent well biasing methods.
    Type: Grant
    Filed: October 20, 2009
    Date of Patent: May 8, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Akira Goda, Tomoharu Tanaka, Krishna Parat, Prashant Damle, Shafqat Ahmed
  • Fully depleted silicon-on-insulator CMOS logic
    Patent number: 8174081
    Abstract: A extractor implanted region is used in a silicon-on-insulator CMOS memory device. The extractor region is reversed biased to remove minority carriers from the body region of partially depleted memory cells. This causes the body region to be fully depleted without the adverse floating body effects.
    Type: Grant
    Filed: May 3, 2011
    Date of Patent: May 8, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Leonard Forbes
  • Programming in a memory device
    Patent number: 8174897
    Abstract: Methods for programming a memory device and memory devices are provided. According to at least one such method, a selected memory cell is programmed by a series of programming pulses. The series of programming pulses are configured in sets of programming pulses where each set has the same quantity of pulses and each programming pulse in the set has substantially the same amplitude (i.e., programming voltage). The amplitude of the programming pulses of subsequent sets is increased by a step voltage from the previous amplitude.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: May 8, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Violante Moschiano, Marco-Domenico Tiburzi, Giovanni Santin, Giulio G. Marotta
  • Memory module with configurable input/output ports
    Patent number: 8171181
    Abstract: A memory module has one or more memory devices, a controller in communication with the one or more memory devices, and a plurality of input/output ports. The controller is configured to configure each input/output port as an input, an output, or a bidirectional input/output.
    Type: Grant
    Filed: May 5, 2008
    Date of Patent: May 1, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Terry R. Lee, David Ovard, Roy Greeff, Robert N. Leibowitz, Victor Tsai
  • Faster write operations to nonvolatile memory using FSInfo sector manipulation
    Patent number: 8171203
    Abstract: An embodiment of the present invention includes a digital equipment system having a host for sending write commands to write files having sector information and having a controller device responsive to the commands for writing and updating FSInfo sector information. The controller controls a nonvolatile memory system organized into blocks, each block including a plurality of sector locations for storing sector information, a particular free block, designated for storing FSInfo sector information. Upon updating of the FSInfo sector, the updated FSInfo sector information is written to a next free sector of the dedicated block thereby avoiding moving the sectors of the particular block to another block, hence, improving system performance.
    Type: Grant
    Filed: December 19, 2003
    Date of Patent: May 1, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Petro Estakhri, Sam Nemazie
  • NAND flash content addressable memory
    Patent number: 8169808
    Abstract: NAND architecture non-volatile content addressable (CAM) memory devices and methods are described that allows for high density, low cost CAM devices. In addition, the NAND architecture non-volatile CAM memory operates with reduced power consumption characteristics for low power and portable applications. In one NAND architecture non-volatile CAM memory embodiment a wired NOR match line array is utilized. In another embodiment a NAND match line array is shown. In yet other embodiments, hierarchal addressing, hash addressing, tree search and algorithmic/hardware engine based search is detailed utilizing both conventional NAND architecture non-volatile Flash memory arrays and dedicated NAND architecture CAM arrays utilizing wired NOR and wired NAND match lines.
    Type: Grant
    Filed: January 25, 2008
    Date of Patent: May 1, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Frankie F. Roohparvar
  • Sensing for all bit line architecture in a memory device
    Patent number: 8169830
    Abstract: Methods for sensing, memory devices, and memory systems are disclosed. One such method for sensing includes charging bit lines of an all bit line architecture to a precharge voltage, selecting a word line, and performing a sense operation on the bit lines. After the sense operation on the memory cells of the first selected word line is complete, the precharge voltage is maintained on the bit lines while a second word line is selected.
    Type: Grant
    Filed: September 17, 2009
    Date of Patent: May 1, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Violante Moschiano, Giovanni Santin, Tommaso Vali
  • Methods of directly accessing a mass storage data device
    Patent number: 8166488
    Abstract: Methods of directly accessing a mass storage data device without communicating through an operating system layer are useful in recovering information previously stored in the mass storage device.
    Type: Grant
    Filed: January 16, 2007
    Date of Patent: April 24, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Neal Anthony Galbo, Berhanu Iman, Ngon Le
  • Fabrication of finned memory arrays
    Patent number: 8163610
    Abstract: Methods and apparatus are provided. For an embodiment, a plurality fins is formed in a substrate so that the fins protrude from a substrate. After the plurality fins is formed, the fins are isotropically etched to reduce a width of the fins and to round an upper surface of the fins. A first dielectric layer is formed overlying the isotropically etched fins. A first conductive layer is formed overlying the first dielectric layer. A second dielectric layer is formed overlying the first conductive layer. A second conductive layer is formed overlying the second dielectric layer.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: April 24, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Seiichi Aritome
  • Reduction of punch-through disturb during programming of a memory device
    Patent number: 8164950
    Abstract: A punch-through disturb effect in a memory device can be reduced by biasing a selected word line at a program voltage to program a selected memory cell, biasing word lines on the drain side of the series string with a Vpass voltage, turning off an adjacent memory cell to the selected memory cell, and biasing remaining word lines on the source side of the turned-off memory cell with a Vlow voltage that is less than Vpass.
    Type: Grant
    Filed: May 12, 2010
    Date of Patent: April 24, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Alessandro Torsi, Carlo Musilli, Seiichi Aritome
  • Flash memory architecture with separate storage of overhead and user data
    Patent number: 8161229
    Abstract: A memory device has a plurality of dedicated data blocks for storing only user data and a plurality of dedicated overhead blocks for storing only overhead data. Current overhead segments of a dedicated overhead block can be consolidated and moved to a new dedicated overhead block.
    Type: Grant
    Filed: June 22, 2009
    Date of Patent: April 17, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Petro Estakhri, Siamack Nemazie
  • Reducing effects of program disturb in a memory device
    Patent number: 8159879
    Abstract: A method for programming that biases a selected word line with a programming voltage. An unselected word line on the source side and an unselected word line on the drain side of the selected word line are biased at a pass voltage that is less than the normal pass voltage. These unselected word lines are both located a predetermined distance from the selected word line. The remaining word lines are biased at the normal pass voltage.
    Type: Grant
    Filed: February 8, 2011
    Date of Patent: April 17, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Seiichi Aritome
  • Methods of storing multiple data-bits in a non-volatile memory cell
    Patent number: 8159875
    Abstract: Methods of storing multiple data-bits in a non-volatile memory cell are carried out by trapping carriers in a composite trapping layer formed over a tunnel insulator layer. The composite trapping layer contains a plurality of band engineered sub-layers providing a plurality of charge trapping layers.
    Type: Grant
    Filed: August 25, 2009
    Date of Patent: April 17, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Arup Bhattacharyya
  • Cell operation monitoring
    Patent number: 8159874
    Abstract: Memory devices adapted to process and generate analog data signals representative of data values of two or more bits of information facilitate increases in data transfer rates relative to devices processing and generating only binary data signals indicative of individual bits. Programming of such memory devices includes programming to a target threshold voltage range representative of the desired bit pattern. Reading such memory devices includes generating an analog data signal indicative of a threshold voltage of a target memory cell. Atypical cell, block, string, column, row, etc. . . . operation is monitored and locations and type of atypical operation stored. Adjustment of operation is performed based upon the atypical cell operation.
    Type: Grant
    Filed: January 22, 2008
    Date of Patent: April 17, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Frankie F. Roohparvar
  • Attachment integrated claims systems and operating methods therefor
    Patent number: 8155979
    Abstract: Systems and methods for processing textual messages which are integrated with one or more digital attachments is described. These systems and methods are useful in the electronic filing and processing of, for example, image data, and of textual data associated with the image data. One particular application of these systems and methods would be for the electronic filing and processing of dental x-rays with patient claim forms.
    Type: Grant
    Filed: January 5, 2007
    Date of Patent: April 10, 2012
    Assignee: Integrated Claim Systems, LLC
    Inventor: Andrew L. DiRienzo
  • Removable storage device
    Patent number: 8151041
    Abstract: Methods and removable storage devices are provided. Some such removable storage devices may include a file specifying a name of a program to be executed automatically by a host, may include settings for a secure storage area, where the settings are user-configurable, may include a secure partition that is not accessible by an operating system of a host, may be configured to cause a health of the removable device to be automatically checked when the removable device is coupled to a host, may be configured to cause a program for formatting the removable device to be executed when the removable device is coupled to a host, or may include a secure partition configured to store information so that formatting/reformatting does not alter the stored information.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: April 3, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Ahuja Gurmukhsingh Ramesh, Senthil Kumar Chellamuthu
  • Version based non-volatile memory translation layer
    Patent number: 8151040
    Abstract: A non-volatile memory and erase block/data block/sector/cluster update and address translation scheme utilizing a version number is detailed that enhances data updating and helps reduce program disturb of the memory cells of the non-volatile memory device. The various embodiments utilize a version number associated with each erase block, data block, sector, and/or cluster. This allows for determination of currently valid data block, sector and/or cluster associated with the logical ID of the data grouping by locating the most recent version associated with the logical ID. With this approach, old data need not be invalidated by programming a valid/invalid flag, avoiding the risk of program disturb in the surrounding data rows.
    Type: Grant
    Filed: June 16, 2010
    Date of Patent: April 3, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Wanmo Wong
  • Dynamic pass voltage for sense operation in a memory device
    Patent number: 8144516
    Abstract: Methods for sensing and memory devices are disclosed. One such method for sensing uses a dynamic pass voltage on at least one adjacent memory cell that is adjacent to a selected memory cell for programming. If the adjacent memory cell is not programmed, the pass voltage is reduced on the adjacent memory cell. The adjacent memory cell can be on the drain side, the source side, or both drain and source sides of the selected memory cell.
    Type: Grant
    Filed: December 3, 2009
    Date of Patent: March 27, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Yijie Zhao, Akira Goda, Jian Li, Haitao Liu