Abstract: A switching current amplifier for stepping motors utilizing a square hysteresis loop transformer to measure the motor winding load current directly, to determine the high and low switching points in reference to the position command signal, to compare the motor winding current to the determined switching points and to provide a switching signal to switch the output devices of the amplifier when the motor winding current reaches the switching points. The square hysteresis loop transformer is constructed to have a high common mode signal rejection.

Abstract: A CMOS amplifier having a pair of CMOS load and amplifying devices connected in series, two parallel pairs of CMOS devices with interconnected gates to form current mirrors and connected to the gate of the load MOS device to compensate the gain for variations in power supply voltage, temperature and transistor parameters, a feedback MOS device having its source-drain path connected between the junction of the load and amplifying MOS and the gate of the amplifying MOS to provide nonlinear, negative feedback, and a resistor connected in parallel with the feedback MOS device to establish an initial self-biasing voltage level for the amplifying MOS below the threshold voltage of the feedback MOS.

Abstract: In a numerically controlled machine includes a first computer which stores command data for a path and derives sets of interpolation point data from said command data for a plurality of points along the path. A second computer stores two sets of interpolation point data from said first computer and extrapolates a set of said stored interpolation point data by incrementing velocity with acceleration and position with velocity using a noncircular high order polynomial to produce a sequence of driver command signals.A timing means provides timing signals to the second computer to determine the number and rate of iterations of drive command signals in said sequence as predetermined by the first computer for each set of interpolation point data.The program execution time in the second computer is reduced by a unique method of multiprecision calculation which requires a carry flip flop for each variable calculated and a sign flip flop for eliminated word segments.

Abstract: In a complementary pair of bipolar transistors, one vertical and one lateral, the vertical transistor includes a heavily doped buried emitter, lightly doped buried graded base and a heavily doped surface collector and the lateral transistor includes a lightly doped substrate base and heavily doped emitter and collector. The lateral transistor's collector isolates the lateral transistor's base from the vertical transistor's collector.This integrated circuit approach includes the I.sup.2 L structure of the present invention and T.sup.2 L devices. The I.sup.2 L transistors are in dielectrically isolated regions with the vertical transistors emitter being connected to the polycrystalline support through a vertical opening in the dielectric isolation.

Abstract: PROM wafers having fuses on raised oxide are reworked by stripping the fuses and connectors, non-selectively etching the oxide layer to form a substantially planar, oxide surface resulting from the differential etching rate of the heavily phosphorus doped raised oxide surface compared to the remainder of lightly doped oxide, increasing the oxide layer thickness and forming new fuses and connectors on the new oxide.

Abstract: The slew rate of an electronic operational amplifier is maximized by inserting additional capacitance calculated according to the equation. ##EQU1## The capacitance may be connected across the amplifier current source to provide additional transient current flowing through the input differential pair and thus increase slew rate without affecting the amplifier's stability.

Abstract: A support for a corner clamp which maintains two trim strips at a ninety degree angle is provided which allows pivoting of the clamped trim from a horizontal plane to a vertical plane. The corner clamp is mounted to the support so that the clamped trim may be rotatably adjusted in their plane.

Abstract: A complementary pair of vertically aligned, inversely operated transistors formed from a P type substrate, a first N type epitaxial layer, a second N type epitaxial layer and a buried, updiffused P type region between the two epitaxial layers. The impurity concentration of the buried region decreases from its junction with the first epitaxial layer to its junction with the second epitaxial layer whose impurity concentration is less than that of the first epitaxial layer. High impurity concentration N type guard ring and P type base ring are diffused simultaneously with the out diffusion of the buried P type region into the second epitaxial layer. The substrate, first epitaxial layer and buried region constitute the emitter, base, and collector of the inverse vertical PNP transistor and the first epitaxial layer, buried region and second epitaxial layer constitute the emitter, base, and collector of the inverse vertical NPN transistor.

Abstract: A current source having two current paths connected as current mirrors with an amorphous material device in one of the current paths which is electrically alterable from a high impedance state to lower high impedance states without switching to a low impedance state. A diode interconnects the amorphous material element to the current path to prevent damage to the current path during electrical alteration of the amorphous material device. The current source is included in a differential amplifier and operational amplifier to provide fine incremental trim or offset adjustment.

Abstract: A holder for supporting a log in a vertical position to be split. The holder is formed of three interconnected horizontally extending support members and an adjustable retainer having a curved collar thereon is slidably mounted on each support member to hold the log in position. A screw or wedge locking means is used to hold the adjustable retainers in the desired position on the support members.

Abstract: A memory array wherein each memory cell includes a pair of threshold resistive elements which switch from a high to a low resistance state when a potential above their respective programmable thresholds is applied. A binary value is stored by creating a threshold difference between the two resistive elements using two different value current sources. The binary value stored is read by applying a ramp potential and determining which threshold resistive element switched states first using a sense latch.

Abstract: A RAM cell having a pair of transistors formed in two adjacent wells laterally separated from each other and surrounded laterally by a common doped polycrystalline semiconductor moat. Dielectrical insulation separate the wells from the moat. The moat is discontinuous, forming thereby a pair of resistors connected together at one end and disconnected at the discontinuity. Surface contacts bridge adjacent areas of the well and the moat which are of the same conductivity type whereby the moat forms the load resistor for the transistor. Each transistor includes a second emitter.First level interconnects include a first interconnect interconnecting an emitter from each transistor, a second interconnect parallel to the first contacting the connected end of the moat resistors, a pair of interconnects each interconnecting the bridge contact of one transistor to the base of the other, and a pair of contacts for the other emitter regions.

Abstract: A free-standing unit for heating air in a U-shaped channel surrounding a fire box having a pair of spaced vertical vents for directing the heated forced air to converge in front of the fire box opening to limit air flow towards said openings. Mesh in the vertical vents directs the forced air downward to be combined with the hot forced air from a bottom horizontal vent. A baffle plate depending from the top of the fire-box adjacent the flue port and an opening along the top of the doors ignite the gases adjacent the top and directs some gases back into the fire. By forcing heated air at a low level and drawing cool air from a high level, the air being heated is of a uniform temperature. A hood extending along the top edge of the fire box opening diverts exiting gases back into the fire box. A thermostatically controlled blower creates the forced air and cools the fire box walls.

Abstract: The Write/Erase lifetime of amorphous memory devices are extended by applying an erase pulse sequence having a first plurality of reset voltage pulses having a maximum amplitude less than the maximum threshold of the device to produce first amplitude current pulses and a second plurality of reset voltage pulses having a maximum amplitude greater than the maximum threshold to produce second amplitude current pulses having an amplitude substantially less than said current pulses. Constant current sources apply the two current pulses when the device threshold is below the maximum voltage amplitude of the first reset voltage pulses and only the second amplitude current pulses when the device threshold exceeds the maximum voltage amplitude of the first reset voltage pulses.

Abstract: A finger ring constructed of an inner annular section threadably attached to an outer annular section, the outer annular section being concentric with the inner section so that no portion of the inner peripheral surface of the outer section is in direct contact with the wearer's finger. Several threaded outer sections may be threadably attached to the inner section, with the outer sections being easily and quickly interchanged.

Abstract: The Write/Erase lifetimes of amorphous memory devices are extended by applying a multilevel erase pulse wherein the first stage has a current amplitude sufficient to heat the crystal filament to the phase change temperature but not to provide the energy for the phase change and erasure of the crystal structure and the second stage has a current amplitude sufficient to heat the filament to remove the crystal structure. Preferably the first stage current is equal to the write current and the second stage is equal to the write current times the ratio of the electrical conductivity of the amorphous conducting state to the apparent conductivity of the crystalline state.

Abstract: A field effect transistor amplifier for use as on the output buffer for semiconductor memories including an electrically alterable element added to an active pull up configuration to allow conversion between active pull up and open drain nonvolatile configurations reversibly or irreversibly. A fusible element or P-N junction device is electrically alterable for irreversible configuration conversion and an amorphous material element is electrically alterable for reversible and irreversible configuration conversion.

Abstract: Complementary MOS devices having spaced guard rings are fabricated by applying an oxide layer to an N substrate with an opening for doping P-type impurities to form a well, applying a nitride layer over a portion of the oxide and of the well portions, doping the area in the well between the nitride and the oxide to form P-type guard rings, masking the well and adjacent portion of the oxide, doping the area between the mask and the exposed nitride layer to form N-type guard rings and exposing the substrate to an oxidizing atmosphere to oxidize the substrate except where covered by the nitride layer. The nitride layer is removed and standard device processing is used to form complementary MOS in the areas previously covered by the nitride.

Abstract: A single circuit board, having a communication interface adapter circuit including I/O and power supply connectors, switches and indicators mounted directly thereto, is mounted to the rear panel of a first housing portion via stand-off and fasteners. The front and rear panels of a first housing portion are parallel to the printed circuit board and include apertures to allow external access to the connectors, switches and indicators. A power supply in a separate housing is mounted to the rear panel of and external to the first housing portion.

Abstract: A control system for an animation stand including a stored program computer for monitoring and storing a plurality of manually produced positions of a camera and a support relative to each other and for calculating a plurality of driver command signals from said stored positions and stored time frame or control data to produce a sequence of motions of said camera and said support relative to each other. A manually induced velocity vector is used by the computer to calculate driver command signals to effectuate the manually produced positions. Each axis of motion per time frame may be individually manually produced.