Abstract: An innovative method and system of performing multiway branch operations on a microprocessor architecture which supports single instruction multiple data (SIMD) operations is provided. A computer processor includes a branch condition register, a graphic status register, a displacement register, a branch offset register, a program counter register and circuit logic responsive to a multiway branch opcode. Bitwise AND logic coupled to the branch condition register and the graphic status register performs a bitwise logical AND between a mask contained in the branch condition register and multiple comparison results contained in the graphic status register. An output port from bitwise logical AND is coupled to a constant array and selects a set of constant values based on the bitwise logical AND result value.