Patents Represented by Attorney, Agent or Law Firm Leo V. Novakoski
  • Patent number: 6111205
    Abstract: A connector for coupling high frequency signals between devices includes a substrate having an array of vias for coupling a reference voltage to reference voltage traces that extend along the substrate surface between the devices. Signal traces including device pads for coupling signals to and from the devices alternate with the reference voltage traces. The widths of the reference voltage traces are varied to maintain a substantially constant separation between the reference voltage trace and an adjacent signal trace.
    Type: Grant
    Filed: October 28, 1997
    Date of Patent: August 29, 2000
    Assignee: Intel Corporation
    Inventors: Michael Leddige, John Sprietsma
  • Patent number: 6112265
    Abstract: A system and method is provided for enhancing the efficiency with which commands from and initiating device to a resource are processed by the resource. The system includes a command queue, a plurality of command reorder slots coupled to the command queue, and command selection logic coupled to the resource and the command reorder slots. Commands ready for processing are loaded into the command reorder slots, and the command selection logic applies an efficiency criterion to the loaded commands. A command meeting the efficiency criterion is transferred to the resource for processing. The system may also include response reordering logic, which is coupled to the command reorder logic. The response reorder logic returns to original command order data provided in response to reorder read commands.
    Type: Grant
    Filed: April 7, 1997
    Date of Patent: August 29, 2000
    Assignee: Intel Corportion
    Inventors: David J. Harriman, Brain K. Langendorf, Robert J. Riesenman
  • Patent number: 6112247
    Abstract: A method is provided that allows a networked computer to generate a routable response to a status query without invoking its communication protocol stack. The computer is provided with a network controller that includes query detection and data routing modules. A message received by the network controller is scanned for a recognition code that identifies the message as a status query. A status query message includes a prototype response that includes the IP data necessary to respond to the query. When a message is identified as a status query, the data routing module extracts network routing data and the prototype response from the message and generates a routable response packet from the extracted information. Status data may be added to the routable response packet by the data routing module.
    Type: Grant
    Filed: November 18, 1997
    Date of Patent: August 29, 2000
    Assignee: Intel Corporation
    Inventor: Steven D. Williams
  • Patent number: 6108781
    Abstract: A method is provided for selecting a bootstrap processor from among the processors of a multiprocessor system. Each processor has an identity code and each processor that is eligible to serve as the bootstrap processor sends an election message to processors having lower valued identity codes. If no processor having a lower valued identity code responds to the election message, the processor that originated the election message designates itself as the bootstrap processor and sends a message to all processors indicating itself as the bootstrap processor.
    Type: Grant
    Filed: February 23, 1999
    Date of Patent: August 22, 2000
    Assignee: Intel Corporation
    Inventor: Muthurajan Jayakumar
  • Patent number: 6084426
    Abstract: A compensated CMOS receiver includes an inverter, at least one compensation transistor coupled between a first voltage and the output of the inverter, a comparison circuit coupled to the output of the inverter, and a control circuit coupled to the comparison circuit and the compensation transistor. When the receiver is driven to a calibration state, the comparison circuit generates an output signal that reflects the difference between the inverter's output voltage and a switch-point reference. The control circuit adjusts the one or more compensation transistors according to the difference signal generated by the comparison circuit.
    Type: Grant
    Filed: December 24, 1997
    Date of Patent: July 4, 2000
    Assignee: Intel Corporation
    Inventor: Michael J. Allen
  • Patent number: 6081890
    Abstract: A firmware system comprises a legacy firmware module and a native firmware module written for native and legacy instruction set architectures (ISAs), respectively. A data structure is associated with the legacy firmware module to provide access to one or more legacy routines through a first dispatcher. The native firmware nodule includes a prologue routine. The prolog routine locates the data structure associated with the legacy firmware module and initializes it to provide a link between the first and second firmware modules.
    Type: Grant
    Filed: November 30, 1998
    Date of Patent: June 27, 2000
    Assignee: Intel Corporation
    Inventor: Sham Datta
  • Patent number: 6067643
    Abstract: A programmable apparatus is provided that performs real time observation of signals associated with operation of a graphics controller. The apparatus includes a command interface that receives event-monitoring instructions and an observation module that is coupled to resources of the graphics controller. The observation module monitors signals generated by one or more resources in the graphics controller system and processes these signals according to the received event-monitoring instructions.
    Type: Grant
    Filed: December 24, 1997
    Date of Patent: May 23, 2000
    Assignee: Intel Corporation
    Inventor: E. Theodore L. Omtzigt
  • Patent number: 6061265
    Abstract: A system for storing data on a magnetic medium using spin polarized electron beams is provided. The system includes a source of spin polarized electrons and a storage medium disposed a selected distance from the source. The storage medium has a plurality of storage locations, each of which includes a layer of a first non-magnetic material, a layer of magnetic material deposited on the first non-magnetic material, and layer of a second non-magnetic material deposited on the magnetic material. The second material is included to scatter spin polarized electrons from the source into an interaction volume of the magnetic material. An electron optics system directs the source of spin polarized electrons to one of the plurality of storage locations.
    Type: Grant
    Filed: December 23, 1998
    Date of Patent: May 9, 2000
    Assignee: Intel Corporation
    Inventor: Eric C. Hannah
  • Patent number: 6016542
    Abstract: An apparatus is provided that operates in conjunction with a processor having registers and associated caches and a memory. A load management module monitors loads that return data to the registers, including bus requests generated in response to loads that miss in one or more of the caches. A cache miss register includes entries, each of which is associated with one of the registers. A mapping module maps a bus request to a register and sets a bit in a cache miss register entry associated with the register when the bus request is directed to a higher level structure in the memory system.
    Type: Grant
    Filed: December 31, 1997
    Date of Patent: January 18, 2000
    Assignee: Intel Corporation
    Inventors: Robert Steven Gottlieb, Michael Paul Corwin
  • Patent number: 5991403
    Abstract: A method for encoding MPEG compatible video data for subsequent compression comprises detecting a plurality of frames of video data organized as a GOP, generating an encryption key for the GOP, and encrypting the video data using GOP-synchronized substitution, transposition, and rotation transformations that are parameterized by offsets derived from the generated encryption key.
    Type: Grant
    Filed: December 23, 1996
    Date of Patent: November 23, 1999
    Assignee: Intel Corporation
    Inventors: David Aucsmith, Joseph M. Nardone, Robert Sullivan
  • Patent number: 5963944
    Abstract: A system is provided in which autonomous agents manage the distribution of data and index information among the nodes of a computer network. The system comprises a network of computer nodes, each of which includes a data store and an agent interface for execution of the autonomous agents. The autonomous agents move independently among the network nodes, using the agent interface at each node they visit to execute their functions. Various types of agents are employed to implement different functions in the system. Index agents transfer index fields to and from the data stores of the network nodes according to a transfer criterion that is biased to aggregate index blocks into index files on one or more network nodes. Replication agents replicate index files on different nodes to make the system robust against node loss.
    Type: Grant
    Filed: December 30, 1996
    Date of Patent: October 5, 1999
    Assignee: Intel Corporation
    Inventor: Robert Adams
  • Patent number: 5933459
    Abstract: A dual reference voltage input receiver comprises a latch, comparison logic for determining the voltage level of a data signal relative to that of first and second reference voltage levels, and selection logic for determining which of the reference voltage levels is operative for a given data interval, e.g. clock cycle. The latch couples the determined voltage level of the data signal to a subsequent stage and to the selection logic for determining the operative reference voltage level in the next data interval. In one embodiment of the invention, the comparison logic includes first and second comparators for comparing the data signal with first and second reference voltages, and the selection logic is a MUX having its data inputs coupled to the comparators' outputs and its selection input coupled to the data output of the latch.
    Type: Grant
    Filed: December 30, 1996
    Date of Patent: August 3, 1999
    Assignee: Intel Corporation
    Inventors: Gary Saunders, Michael J. Allen
  • Patent number: 5904733
    Abstract: A method is provided for selecting a bootstrap processor from among the processors of a multiprocessor system. Each processor has an identity code and each processor that is eligible to serve as the bootstrap processor sends an election message to processors having lower valued identity codes. If no processor having a lower valued identity code responds to the election message, the processor that originated the election message designates itself as the bootstrap processor and sends a message to all processors indicating itself as the bootstrap processor.
    Type: Grant
    Filed: July 31, 1997
    Date of Patent: May 18, 1999
    Assignee: Intel Corporation
    Inventor: Muthurajan Jayakumar
  • Patent number: 5861893
    Abstract: A graphics controller enhances concurrency among multiple pipelines, provides high throughput to graphics resources between 2D and 3D pipelines spawned by an application, and provides low latency for 2D pipelines spawned by an operating system. The graphics controller includes a command parser, arbitration logic, a BLTBIT engine having first and second operating registers. Graphics commands from the application are routed through the command processor, while graphics commands from the operating system are written to the second operating register. Access signaling bits associated with each operating register for communicating between the arbitration logic and the application and operating system. Graphics commands from application-spawned pipelines are coupled through the command parser to specified graphics resources, including the first operating register. An arbitration scheme assigns higher priority to BLTBIT engine accesses initiated by pipelines spawned by the operating system.
    Type: Grant
    Filed: May 27, 1997
    Date of Patent: January 19, 1999
    Assignee: Intel Corporation
    Inventor: Jay J. Sturgess
  • Patent number: 5842217
    Abstract: A method is provided for identifying compound terms in a document that is represented by a stream of tokens. The stream of document tokens is scanned for an initial term associated with a compound term and a compound term template is accessed when the initial term is identified. The template includes content, retention, and token specifications for the compound term. The stream of tokens is compared with the template, and when the stream matches the content specification of the template, a token representing the compound term is tagged according to the retention specification and added to the stream of tokens. The tagged token is stopped according to the retention specification represented by its tag.
    Type: Grant
    Filed: December 30, 1996
    Date of Patent: November 24, 1998
    Assignee: Intel Corporation
    Inventor: John Light
  • Patent number: 5778363
    Abstract: A method is provided for specifying the representation of a document and determining the relevance of the document according to an externally defined topic profile. The topic profile includes one or more compound terms having a positive correlation with the topic of interest. Each compound term has a specified form such as capitalization, punctuation, number, or adjacency relation, that is either ignored by conventional indexing processes or requires substantial data overhead to track. The compound terms of the topic profile are tagged to indicate how corresponding terms are treated when identified in a document being analyzed. Application of the topic profile to a document generates a document representation in which compound terms present in the document are retained in their specified form. A similarity function between the document representation and the topic profile is calculated, and the result is compared to a relevance threshold associated with the topic profile.
    Type: Grant
    Filed: December 30, 1996
    Date of Patent: July 7, 1998
    Assignee: Intel Corporation
    Inventor: John Light
  • Patent number: 5660930
    Abstract: A [(Pt/Co/Pt)/Pd] multilayer thin film (40) provides improved perpendicular anisotropy and magnetic coercivity relative to Pt/Co multilayer thin films (10) without reducing the Kerr rotations provided by the component Pt/Co layers (44, 48, 46). [(Pt/Co/Pt)/Pd] multilayer thin films (40) comprise a substrate (26), an optional underlayer (110) including a crystallographically textured layer (114) of Pt and a crystallographically textured layer (116) of Pd, and several quadlayers (42) of Pt, Co, and Pd forming a periodic array (43) in the direction of the normal to the substrate (26). Each quadlayer (42) of the periodic array (43) typically comprises a first layer (44) of Pt atoms approximately one to two atomic monolayers thick, a layer (46) of Co between one and three atomic monolayers thick, a second layer (48) of Pt of substantially the same thickness as the first layer (44) of Pt, and a layer (50) of Pd that is at least as thick as the Pt layers.
    Type: Grant
    Filed: April 4, 1994
    Date of Patent: August 26, 1997
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Gerardo A. Bertero, Robert Sinclair
  • Patent number: 5632028
    Abstract: A system and method provides hardware support for fast software emulation of unimplemented instructions using issue trap logic that determines the instruction type and parameter fields of an unimplemented instruction when an exception is triggered and uses the fields to branch directly to emulation code specific to an unimplemented instruction having the determined instruction type and parameter fields.
    Type: Grant
    Filed: March 3, 1995
    Date of Patent: May 20, 1997
    Assignee: HaL Computer Systems, Inc.
    Inventors: Shalesh Thusoo, Farnad Sajjadian, Jaspal Kohli, Niteen A. Patkar
  • Patent number: 5610847
    Abstract: A ratiometric Fourier analyzer is provided for determining the frequency components of the output waveforms of electronic circuits by eliminating errors due to aliasing without increasing the time necessary for analysis. Ratiometric Fourier analyzers in accordance with the present invention detect values of an output waveform from a circuit simulator at time intervals selected according to features of the output waveform being analyzed. A functional representation of the output waveform over each interval is generated using a polynomial fit to the detected values of the waveform, and a Fourier integral for each frequency of interest is calculated for interval using the functional representation of the waveform. The Fourier integrals are then summed over the intervals of the output waveform to yield the Fourier coefficient at a given frequency for the output waveform.
    Type: Grant
    Filed: October 28, 1994
    Date of Patent: March 11, 1997
    Assignee: Cadence Design Systems, Inc.
    Inventor: Kenneth S. Kundert
  • Patent number: 5570238
    Abstract: A thermally compensating lens mount (40) comprises an axially symmetric housing (42) that is formed from an inner layer of a first material (44) having a low coefficient of thermal expansion (CTE) to an outer layer of a second material (46) having a high CTE. The longitudinal cross-section of the housing (42) has a barrel shaped geometry along the symmetry axis (47) so that differential thermal expansion of the first and second materials (44, 46) decreases the length of the housing (42) along its axis of symmetry (47) by an amount determined by the CTEs of the inner and outer layers (44, 46), their thicknesses, and the geometry of the barrel shape.
    Type: Grant
    Filed: March 31, 1995
    Date of Patent: October 29, 1996
    Assignee: Lockheed Missiles & Space Company, Inc.
    Inventor: David F. Leary