Abstract: A switched capacitor input circuit that reduces nonlinear input current due to input switch charge injection. The addition of a shunt capacitor with a series switch to signal ground at the input switch of a sampling network is used to sample and hold the input switch charge injection. This input switch charge injection can then be returned as input switch channel charge during the next sampling phase eliminating the need for the input signal to supply this charge.

Abstract: A clock multiplier/jitter attenuator circuit provides a stable clock which is a multiple frequency of the average frequency of an external digital data stream. The external data is written into successive storage cells of a FIFO at its own clock rate and read out of the FIFO at the rate of an internal clock signal which is formed by frequency dividing the stable clock. The relative locations of the cell being written into and the cell being read out of are determined at periodic time intervals, and these relative locations are used to adjust the frequency of an internal oscillator which generates the stable clock. The instantaneous jitter on the digital data stream is absorbed by the FIFO.

Abstract: A high speed feedback amplifier is frequency compensated utilizing circuitry that does not cause distortion in the amplifier nor does it limit the slew rate of the amplifier. In one embodiment compensation circuitry drives one side of the compensation capacitor forcing the signal voltage across the compensation capacitor to zero while still providing bandwidth compensation. Since no current gets driven into the capacitor, no distortion or slew limitations are created by the compensation. In a second embodiment the voltage across the compensation capacitor is allowed to change, however the signal current for the compensation capacitor is supplied by a linear charging circuit which removes this charging requirement from the amplifier. Therefore, as in the first embodiment, no distortion or slew limitation is created by the addition of the frequency compensation.

Abstract: An amplifier with controlled output impedance has a first output connected to the inverting input of the amplifier, and a second output, which forms the output of the amplifier, connected through a feedback conductance to the inverting input of the amplifier. A input conductance is connected from the inverting input to ground, and the input signal is connected to the positive input of the amplifier. The first and second outputs are provided by first and second current output stages. The currents provided by the first and second output stages are proportional to each other by a predetermined ratio. By proper selection of this predetermined ratio and the feedback and input conductances the desired output impedance and overall gain of the amplifier into a given load can be achieved.

Abstract: A wide bandwidth transconductance amplifier utilizing internal feedback is stabilized over a wide range of output currents. A compensation driver circuit senses the output current in the amplifier and feeds it back through a compensation capacitor. This keeps the bandwidth of the amplifier constant and optimally stabilized over a 16 to 1 range in output current. This compensation scheme eliminates compensation compromises that can limit the useful dynamic range of transconductnce amplifiers while offering a wide bandwidth low distortion transconductance with high output impedance over frequency.

Abstract: An oversampling analog-to-digital modulator includes an analog loop filter which has a first integrator stage which operates as a continuous time integrator. the second, third, and fourth integrator stages are discrete time or sampling integrators. The continuous time first integrator provides the required thermal noise characteristics of the loop filter while the discrete time integrator stages provide loop stability and transfer characteristics which are advantageous to the overall operation of the analog-to-digital modulator.

Abstract: An oversampling analog-to-digital modulator includes an analog loop filter which has a first integrator stage which is a single-ended integrator. The second, third, and fourth integrator stages are fully-differential integrators. The first integrator provides the required thermal noise characteristics of the loop filter with only one feedback capacitor which is external to the integrated circuit chip, while the fully-differential integrator stages provide improved suppression of charge injection transients.

Abstract: The quantization noise in a delta-sigma converter can produce correlated noise when the converter is operating. This correlated noise can produce tones in the frequency band of interest. In a departure from conventional wisdom these tones are substantially eliminated by the degration of the signal-to-noise ratio at the input of the comparator in the delta-sigma converter. In the preferred embodiment this degradation of the signal-to-noise ratio is accomplished by attenuating the input signal to the comparator such that the input signal becomes comparable to the noise generated in the input stage of the comparator.

Abstract: A linear power amplifier having differential push-pull outputs, in which each output consists of an upper and a lower output transistor, includes cross-coupling transistors coupled between the gate of each of the output transistors and a reference voltage such that when the cross-coupled transistor is made conductive, it acts to turn off its associated output transistor. Each of the cross-coupled transistors is controlled by the voltage at the gate of the corresponding output transistor at the other of the differential outputs. Thus, the cross-coupling transistors insure that only one of the upper output transistors is on at one time and only one of the lower output transistors is on at any one time. These cross-coupling transistors operate in conjection with output stage shutoff circuitry to control the current wasted in the output stages of the linear power amplifier by ensuring that the output transistors at each output are not both conducting a significant amount of current at any one time.

Abstract: A semiconductor capacitor for use in an analog-to-digital converter includes two parallel connected capacitors with separate lower plates (44) and (46) fabricated of polycrystalline silicon and upper plates (52) and (54) also fabricated of polysilicon. The plates are separated by capacitive oxide dielectric structures (48) and (50). They are interconnected such that the lower plate (44) of one capacitor is connected to the upper plate (54) of the other capacitor and the lower plate (46) of the other capacitor is connected to the upper plate (52) of the first capacitor. With such a configuration, the odd ordered non-linearities contributing to the voltage coefficient errors are cancelled.

Abstract: An option select circuit for a dialer includes an internal address generator (20) for generating an address pattern, which, in a set up mode, is output from a multiplexer (14) to I/O pins (10). The pins (10) are selectively hardwired through an interface circuit (24) back to address input pins (50) and (52) for input to a decorder (28). The decoder (28) decodes the selected address for input to a PLA (30). This allows selection of various functions in a function generator (12) for operation in the normal dialer mode. The interface circuit (24) comprises hardwire connections (54) and (56).

Abstract: Method of operation of an A/D converter having an oversampling front end quantizer coupled to a digital decimation filter. The method includes setting an effective feedback reference voltage to a value that is a predetermined factor greater than a specified maximum analog input voltage; and increasing the gain of the digital decimation filter by an amount substantially equal to the predetermined factor. In accordance with another aspect of the invention, an A/D converter includes a delta-sigma modulator wherein the full-scale analog input voltage is set below a maximum effective feedback reference voltage by a predetermined factor; and, the impulse-response coefficients of a digital decimation filter coupled to the output of the delta-sigma modulator are selected to provide full-scale digital output when a full-scale analog input voltage is applied to the analog voltage input.

Abstract: A method and circuitry for time-sharing a digitally-programmable capacitive element, particularly in conjunction with a switched-capacitor filter circuit. The method includes: selecting a first capacitance value for the capacitive element; initializing the charge on the capacitive element; connecting the capacitive element to first preselected nodes of an electronic circuit; disconnecting the capacitive element from the first preselected nodes of after any charge transfer has substantially been completed; changing the capacitance of the capacitive element to a new desired value; initializing the charge on the capacitive element; and then connecting the capacitive element to other preselected nodes of the electronic circuit. A biquad switched-capacitor filter circuit is configured to use such method in its operation.

Abstract: A golf putting teaching aid for helping a golfer learn proper accelerated putting includes a rectangular putting surface having a putter path line located lengthwise down the center of the putting surface to indicate the proper path of a putter during the putting stroke. A plurality of squaring lines are disposed perpendicular to the putter path at different distances from the cup. These squaring lines serve as a visual aid for the golfer to indicate the proper orientation of the putter head when it strikes the ball, i.e., perpendicular to the path of the golf ball. A stroke length ruler is locatable along an edge of the putting surface and has indicia for aligning the stroke length ruler with the position of the golf ball and for indicating the proper backswing and follow-through in relation to the distance of each putt.

Abstract: A clock multiplier/jitter attenuator circuit provides a stable clock which is a multiple frequency of the average frequency of an external digital data stream. The external data is written into successive storage cells of a FIFO at its own clock rate and read out of the FIFO at the rate of an internal clock signal which is formed by frequency dividing the stable clock. The relative locations of the cell being written into and the cell being read out of are determined at periodic time intervals, and these relative locations are used to adjust the frequency of an internal oscillator which generates the stable clock. The instantaneous jitter on the digital data stream is absorbed by the FIFO.

Abstract: Method and circuitry for generating precise reference voltages. The method includes generation of a stair-step voltage waveform wherein the voltage changes from step to step are virtually identical. The stair-step voltage waveform generation includes charging a first capacitor to an available voltage reference and then transferring the charge to a larger second capacitor. This charging and subsequent charge transferring is repetitively performed to generate the stair-step waveform across the terminals of the larger capacitor. Sample-and-hold circuits are used to sample the steps of the stair-step voltage waveform and thereby provide a set of DC reference voltages. The circuitry is suitable for fabrication in a CMOS monolithic integrated circuit and can be used in conjunction with flash A/D converters.

Abstract: A sampling amplifier (22) consisting of a series combination of a signal input terminal (12), a first capacitor (C1), a first amplifier (A1), a second capacitor (C2), a second amplifier (A2), and a signal output terminal (VOUT2) is able to sample at a higher frequency by providing a low impedance path between the signal output terminal (VOUT2) and a junction (VOUT1) between the first amplifier (A1) and the second capacitor (C2) to quasi auto-zero the amplifier between samples.

Abstract: A delay circuit which is insensitive to variations in power supply voltage, which is temperature-compensated, and which is suitable for fabrication in a monolithic integrated circuit includes circuitry for charging a capacitive element through a resistive element from GND toward the power supply voltage. The voltage across the capacitive element is compared to a reference voltage by a voltage comparator, and the voltage comparator generates an output signal when the voltage on the capacitor becomes greater than the reference voltage. The reference voltage for the comparator is generated by a resistor divider connected between GND and the power supply voltage. Inasmuch as the reference voltage varies with changes in the power supply voltage in such a manner as to be maintained at a substantially fixed percentage of the power supply voltage, the time delay provided by the delay circuit is essentially independent of variations in power supply voltage.

Abstract: Method for reducing deleterious effects of electrical noise in an analog-to-digital converter wherein both the analog and digital circuitry of the A/D converter are embodied in the same integrated circuit. The method includes sampling an analog input voltage with a first clock signal, generating a second clock signal that is delayed with respect to the first clock signal, and using the second clock signal as a clock for the digital circuitry. In accordance with another aspect of the invention, the method for reducing effects of noise in an A/D converter wherein such noise is generated by a digital decimation filter includes synchronously pipelining the arithmetic operations of the digital decimation filter.

Abstract: An embedded framing bit pattern in a serial bit stream is located by combining the last bit to arrive of the serial bit stream with a predetermined number of prior bits of the serial bit stream which are spaced apart by the pitch of the bits of the framing bit pattern, and this combination of bits is tested to determine if the combination matches part of the framing bit pattern. If a match does not occur, then the bits which were combined together are changed to a bit pattern that will not result in a match when these bits (except for the eldest bit which is disregarded) is combined again with a new bit of the serial bit stream, no matter what the logic state of the new bit. In this manner all of the bits, as they arrive and are combined and tested, will eventually be changed except the bits which are part of the framing bit pattern.