Patents Represented by Attorney Lewis and Roca LLP

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  • Method and apparatus for universal program controlled bus architecture
    Patent number: 7915918
    Abstract: An integrated circuit including a programmable logic array with a plurality of logic cells and programmable interconnections to receive input signals and to perform logical functions to transmit output signals. The integrated circuit may also include megacells comprising a plurality of functional blocks receiving inputs and transmitting outputs. The integrated circuit may also include a programmable interconnections subsystem to cascade the megacells. The megacells are coupled to the programmable logic array.
    Type: Grant
    Filed: October 29, 2010
    Date of Patent: March 29, 2011
    Assignee: Actel Corporation
    Inventors: Peter M. Pani, Benjamin S. Ting
  • Photodiode with improved charge capacity
    Patent number: 7910394
    Abstract: A method for forming a photodiode cathode in an integrated circuit imager includes defining and implanting a photodiode cathode region with a photodiode cathode implant dose of a dopant species and defining and implanting an edge region of the photodiode cathode region with a photodiode cathode edge implant dose of a dopant species to form a region of higher impurity concentration than the photodiode cathode impurity concentration.
    Type: Grant
    Filed: April 1, 2008
    Date of Patent: March 22, 2011
    Assignee: Foveon, Inc.
    Inventor: Maxim Ershov
  • Isolated-nitride-region non-volatile memory cell and fabrication method
    Patent number: 7910436
    Abstract: An isolated-nitride-region non-volatile memory cell is formed in a semiconductor substrate. Spaced-apart source and drain regions are disposed in the semiconductor substrate forming a channel therebetween. An insulating region is disposed over the semiconductor substrate. A gate is disposed over the insulating region and is horizontally aligned with the channel. A plurality of isolated nitride regions are disposed in the insulating region and are not in contact with either the channel or the gate.
    Type: Grant
    Filed: June 25, 2010
    Date of Patent: March 22, 2011
    Assignee: Actel Corporation
    Inventor: John McCollum
  • Power-up and power-down circuit for system-on-a-chip integrated circuit
    Patent number: 7911226
    Abstract: A power-up and power-down circuit for an integrated circuit includes a voltage regulator set for a first voltage. A first I/O pad is coupled internally to an input to the voltage regulator and to first internal circuits. The second voltage is externally coupled to the first I/O pad. A second I/O pad is coupled internally to an output of the voltage regulator configured to drive the base of an external transistor. A third I/O pad of the integrated circuit is coupled internally to a reference-voltage input of the voltage regulator. A fourth I/O pad is coupled to a feedback input of the voltage regulator. A fifth I/O pad of the integrated circuit is coupled internally to logic circuitry that controls power-up and power down of the integrated circuit from internal signals including internal signals from a real-time clock circuit disposed on the integrated circuit.
    Type: Grant
    Filed: August 25, 2006
    Date of Patent: March 22, 2011
    Assignee: Actel Corporation
    Inventor: Gregory Bakker
  • Delta sigma modulator for analog-to-digital converter
    Patent number: 7907079
    Abstract: A method for operating a single slope analog-to-digital converter (ADC) includes providing a ramp generator to provide at least one voltage-ramp segment; applying delta-sigma modulation to the voltage-ramp generator to generate a delta-sigma modulated voltage ramp; operating a digital counter synchronously with the voltage-ramp generator; comparing the delta-sigma modulated voltage-ramp to an input voltage; and latching a count from the digital counter in response to the output of the comparator.
    Type: Grant
    Filed: December 9, 2008
    Date of Patent: March 15, 2011
    Assignee: Foveon, Inc.
    Inventors: Brian Jeffrey Galloway, Andrew Cole
  • Reduced-edge radiation-tolerant non-volatile transistor memory cells
    Patent number: 7906805
    Abstract: An edgeless one-transistor flash memory array includes transistors that have two polysilicon gate layers that overlay an active region. The bottom polysilicon gate layer is electrically isolated. The memory is configured such that current passes from drain to source under the bottom polysilicon layer, such that it does not approach a field oxide region. An edgeless two-transistor programmable memory includes memory cells that have two active devices. Two polysilicon gate layers overlay two active regions and are shared between the two active devices. One of the devices is used to program and erase the cell while the other used as a programmable switch in a programmable logic device. The bottom polysilicon gate layer is electrically isolated. The memory is configured such that current passes from drain to source under the bottom polysilicon layer, such that it does not approach a field oxide region.
    Type: Grant
    Filed: August 22, 2008
    Date of Patent: March 15, 2011
    Assignee: Actel Corporation
    Inventors: Michael Sadd, Fethi Dhaoui, John McCollum, Richard Chan
  • Non-volatile two-transistor programmable logic cell and array layout
    Patent number: 7898018
    Abstract: A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.
    Type: Grant
    Filed: January 26, 2009
    Date of Patent: March 1, 2011
    Assignee: Actel Corporation
    Inventors: Fethi Dhaoui, John McCollum, Vidyadhara Bellippady, Zhigang Wang
  • Field programmable gate array and microcontroller system-on-a-chip
    Patent number: 7886130
    Abstract: A system-on-a-chip integrated circuit has a field programmable gate array core having logic clusters, static random access memory modules, and routing resources, a field programmable gate array virtual component interface translator having inputs and outputs, wherein the inputs are connected to the field programmable gate array core, a microcontroller, a microcontroller virtual component interface translator having input and outputs, wherein the inputs are connected to the microcontroller, a system bus connected to the outputs of the field programmable gate array virtual component interface translator and also to the outputs of said microcontroller virtual component interface translator, and direct connections between the microcontroller and the routing resources of the field programmable gate array core.
    Type: Grant
    Filed: December 29, 2008
    Date of Patent: February 8, 2011
    Assignee: Actel Corporation
    Inventors: Arunangshu Kundu, Arnold Goldfein, William C. Plants, David Hightower
  • Flash-based FPGA with secure reprogramming
    Patent number: 7885122
    Abstract: A flash-based programmable integrated circuit includes programmable circuitry, a flash memory array coupled to the programmable circuitry for configuring it, flash programming circuitry for programming the flash memory array, and an on-chip intelligence, such as a microcontroller or state machine, coupled to the programming circuitry to program the flash memory from off-chip data supplied via an I/O pad, or to refresh the data stored in the flash memory to prevent it from degrading.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: February 8, 2011
    Assignee: Actel Corporation
    Inventors: Joel Landry, William C. Plants, Randall Sexton
  • PLD providing soft wakeup logic
    Patent number: 7884640
    Abstract: A programmable logic device (PLD) with a plurality of programmable regions is disclosed. Some of the programmable regions have switch power or ground supplies to allow them to be put into a low-power state in one or more low-power modes. At least one of the programmable regions always remains on during the low-power modes to enable the user to design custom PLD power management logic that may be placed in the always-on programmable region.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: February 8, 2011
    Assignee: Actel Corporation
    Inventors: Jonathan W Greene, Gregory Bakker, Vidyadhara Bellippady, Volker Hecht, Theodore Speers
  • Single event transient mitigation and measurement in integrated circuits
    Patent number: 7884636
    Abstract: A method for single event transient filtering in an integrated circuit device is described. The device comprises three sequential elements, each having a data input and a data output with each of the three data outputs coupled to one of three inputs of a voting gate. The method comprises generating first and second nominally equivalent logic signals in first and second SET domains, converting the first and second nominally equivalent logic signals into first, second and third nominally equivalent data channels, and transmitting the first, second and third nominally equivalent data channels to the data inputs of the first, second and third sequential elements.
    Type: Grant
    Filed: July 1, 2010
    Date of Patent: February 8, 2011
    Assignee: Actel Corporation
    Inventors: Sana Rezgui, John McCollum, Jih-Jong Wang
  • Programmable logic device adapted to enter a low-power mode
    Patent number: 7886261
    Abstract: A programmable logic integrated circuit device adapted to enter a low-power mode is described. The integrated circuit device includes a programmable logic block, a first low-power mode control circuit programmed into a portion of the programmable logic block, a second low-power mode control circuit, and a low-power enable input coupled to the first low-power mode control circuit and the second low-power mode control circuit. This arrangement allows the programmable logic integrated circuit device to transition into and out of low-power mode in response to a single signal from system control logic, so that the system control logic can be designed without detailed understanding of the inner workings of the programmable logic integrated circuit device or its programmed design.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: February 8, 2011
    Assignee: Actel Corporation
    Inventors: Kenneth Irving, Vishal Aggrawal, Prasad Karuganti
  • Solid composition having enhanced physical and electrical properties
    Patent number: 7870887
    Abstract: A method of making a treating wash includes mixing brass granules with acetone, mixing carbon nanotube material, iron pyrite granules and copper granules in the acetone brass mixture, and straining the liquid from the remaining solid material. Methods of treating materials such as brass granules, iron pyrite granules, carbon nanotube material, and brass granules comprises washing the materials in the treating wash, followed by straining and drying the materials.
    Type: Grant
    Filed: April 7, 2010
    Date of Patent: January 18, 2011
    Assignee: Kryron Global, LLC
    Inventor: John M. Bourque
  • Flexible carry scheme for field programmable gate arrays
    Patent number: 7872497
    Abstract: A fast, flexible carry scheme for use in clustered field programmable gate array architectures is described. Each cluster has a cluster carry input node, a cluster carry output node, a cluster carry output circuit having an output coupled to the cluster carry output node, a first input coupled to the cluster carry input node, and a second input and a plurality of logic modules each comprising a logic function generator circuit coupled to a carry circuit. The logic modules are coupled in a series carry arrangement between the cluster carry input node and the second input of the cluster carry output circuit such that the least significant bit of an arithmetic logic circuit can be programmably placed in any of the logic modules.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: January 18, 2011
    Assignee: Actel Corporation
    Inventor: William C. Plants
  • Solid composition having enhanced physical and electrical properties
    Patent number: 7870886
    Abstract: A method of making a treating wash includes mixing brass granules with acetone, mixing carbon nanotube material, iron pyrite granules and copper granules in the acetone brass mixture, and straining the liquid from the remaining solid material. Methods of treating materials such as brass granules, iron pyrite granules, carbon nanotube material, and brass granules comprises washing the materials in the treating wash, followed by straining and drying the materials.
    Type: Grant
    Filed: April 7, 2010
    Date of Patent: January 18, 2011
    Assignee: Kryron Global, LLC
    Inventor: John M. Bourque
  • Data comparison methods and apparatus suitable for image processing and motion search
    Patent number: 7864857
    Abstract: A method and apparatus for calculating the quantized difference between a pixel in a current frame and a pixel in a reference frame is disclosed. The apparatus of the present invention generates a “1 of n” significant difference bit output which may easily be logically OR'd with the difference values from other comparisons to determine the maximum difference over an area of pixels.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: January 4, 2011
    Assignee: Teradici Corporation
    Inventor: David V. Hobbs
  • Tunable antenna system
    Patent number: RE42087
    Abstract: An antenna system with at least one tunable dipole element with a length adjustable conductive member disposed therein that enables the antenna to be used over a wide range of frequencies. The element is made of two longitudinally aligned, hollow support arms made of non-conductive material. Disposed longitudinally inside each element is a length adjustable conductive member electrically connected at one end. In the preferred embodiment, each conductive member is stored on a spool that is selectively rotated to precisely extend the conductive member into the support arm. The support arms, which may be fixed or adjustable in length, are affixed at one end to a rigid housing. During use, the conductive members are adjusted in length to tune the element to a desired frequency.
    Type: Grant
    Filed: January 4, 2006
    Date of Patent: February 1, 2011
    Assignee: Fluid Motion, Inc.
    Inventor: Michael E. Mertel
  • Eighty-one facet brilliant cut diamond
    Patent number: D632205
    Type: Grant
    Filed: June 1, 2010
    Date of Patent: February 8, 2011
    Inventor: Paras Paresh Mehta
  • Proximity sensor
    Patent number: D634661
    Type: Grant
    Filed: March 22, 2010
    Date of Patent: March 22, 2011
    Assignee: Essex Electronics, Inc.
    Inventors: Garrett Y. Kaufman, Peter Kaufman
  • Proximity sensor
    Patent number: D634662
    Type: Grant
    Filed: March 22, 2010
    Date of Patent: March 22, 2011
    Assignee: Essex Electronics, Inc.
    Inventors: Garrett Y. Kaufman, Peter Kaufman