Patents Represented by Attorney Lowell C. Bergstedt
  • Patent number: 4928493
    Abstract: A chill water system combining a storage vessel 10, a multiplicity of ice encapsulating units 11 contained in the vessel and a chiller system 60. The storage vessel contains a volume of glycol and water solution having a freezing point of about twenty six degrees F. The ice encapsulating units 11 comprise sealed containers filled with a deionized water and having a volume of powdered cholesterol therein to serve as an ice nucleating agent to lower the initial ice formation temperature of the unit. The containers have imperfect geometric shape and deformable wall structures to permit an increase in enclosed volume as said water therein freezes. Chiller system 60 is operatively associated with the vessel and cools the glycol and water solution to about twenty six degrees to freeze the water in the containers 11. A topping tank 90 and an inventory tank 93 receive liquid from the storage vessel 10 as the ice encapsulating units 11 freeze and expand in volume.
    Type: Grant
    Filed: February 14, 1989
    Date of Patent: May 29, 1990
    Assignee: Reaction Thermal Systems, Inc.
    Inventors: Thomas A. Gilbertson, Michael R. Meyers, Bruce Kinneberg
  • Patent number: 4905676
    Abstract: A muscle exercise and diagnostic system which includes a lever arm, a mounting arrangement for mounting the lever arm for rotation about a fixed axis, and a connecting arrangement for connecting a selected portion of the human body to the lever arm for rotation with the lever arm about a selected anatomical axis of rotation. The connecting arrangement establishes a fixed tangential mounting relation and a sliding radial mounting relation between the lever arm and the body portion. This permits free radial movement of the connecting arrangement relative to the fixed axis during an exercise motion. A velocity control arrangement is coupled to the lever arm for limiting the maximum permitted rotational velocity to a value predetermined in accordance with a preselected velocity control function which includes measured values of the distances from the point of attachment to the anatomical axis and to the fixed axis. An arrangement is provided for inputting these measured values to a velocity control arrangement.
    Type: Grant
    Filed: March 28, 1986
    Date of Patent: March 6, 1990
    Assignee: Loredan Biomedical, Inc.
    Inventors: Malcolm L. Bond, Philip T. Dempster
  • Patent number: 4889108
    Abstract: A muscle exercise and diagnostic system which includes a lever arm, a mounting arrangement for mounting the lever arm for rotation about a fixed axis, and a connecting arrangement for connecting a selected portion of the human body to the lever arm for rotation about a selected anatomical axis of rotation. The connecting arrangement provides a fixed tangential and sliding mounting to permit free radial movement of the point of attachment of the patient relative to the axis of rotation of the lever arm. A velocity control arrangement coupled to the lever arm limits the velocity in accordance with a preselected velocity control function. The radial distance from the point of attachment to the axis of rotation is measured and used in the velocity control function. Range of motion limits are set in one embodiment by way of a potentiometer for each limit position and by a pushbutton and limit storing arrangement in another embodiment.
    Type: Grant
    Filed: March 20, 1989
    Date of Patent: December 26, 1989
    Assignee: Loredan Biomedical, Inc.
    Inventors: Malcolm L. Bond, Phlip T. Dempster
  • Patent number: 4788420
    Abstract: A system for reading a data record stripe on a credit card which includes an injection molded case including a card guide slot integrally molded into the case near one side thereof and a read head window integrally formed in one sidewall of the card guide slot. A data read head assembly having a read head on a front face thereof is mounted in the read head window and is spring biased toward the wall of the card slot opposite the read head window. A circuit arrangement is coupled to the read head assembly for detecting data signals on a card passing through the slot and converting the data signals to a substantially square wave signal pattern representing binary signal data in the form of positive and negative signal transitions of the square wave signal.
    Type: Grant
    Filed: August 10, 1987
    Date of Patent: November 29, 1988
    Assignee: Verifone, Inc.
    Inventors: Karl Chang, William R. Pape, III, Victor J. Crosetti, Jr., Lance S. Nakamura, Daniel B. C. Leong, Robert K. L. Loui
  • Patent number: 4724521
    Abstract: The present invention provides methods for operating a local terminal which includes a programmable computer so that the terminal executes a pre-arranged application program. More specifically, the present invention provides methods for operating a local terminal according to a pre-arranged application program which is created on a remote computer, then communicated by a communication channel to the local terminal where it is stored for execution.
    Type: Grant
    Filed: January 14, 1986
    Date of Patent: February 9, 1988
    Assignee: Veri-Fone, Inc.
    Inventors: James M. Carron, Brian K. Uechi, Mohammed A. Khan, Clifton W. Royston, III, Jay A. Abel, Bradley J. Ferlane, Robert K. L. Loui, William R. Pape, III
  • Patent number: 4271487
    Abstract: A volatile/non-volatile RAM cell employing a bistable multivibrator with non-volatile, alterable-threshold capacitors coupled to the output terminals thereof to provide backup data storage in a power-down situation. In one embodiment, the non-volatile capacitors each have a non-alterable section and an alterable section, the non-alterable section having either a depletion or an enhancement threshold. The V/NV RAM cell employs a pair of field effect transistors of depletion or enhancement type to couple the non-volatile capacitors to the output terminals. These coupling transistors form with the non-volatile capacitors a pair of nodes. The coupling transistors are biased such that a write voltage signal applied to the gates of the non-volatile capacitors produces a bootstrapped voltage on one of the pair of nodes which is effectively isolated from the output terminals of the cell.
    Type: Grant
    Filed: November 13, 1979
    Date of Patent: June 2, 1981
    Assignee: NCR Corporation
    Inventors: Donald G. Craycraft, George C. Lockwood, Darrel D. Donaldson
  • Patent number: 4176003
    Abstract: An adhesion-enhancing technique for preparing the surface of a polycrystalline silicon body to receive organic photoresist. In an exemplary procedure, the polysilicon is placed in an oxygen plasma chamber operating under rf power of about 90 milliwatts per cubic centimeter of chamber volume and a pressure of approximately 1 torr for 10 minutes to form an adhesion-enhancing oxide monolayer on the polysilicon.
    Type: Grant
    Filed: February 22, 1978
    Date of Patent: November 27, 1979
    Assignee: NCR Corporation
    Inventors: Ronald W. Brower, Jerome Cohen, Peter C. Chen
  • Patent number: 4165923
    Abstract: The present invention relates to a liquid crystal display cell having an alignment film therein. The present invention also relates to a method of aligning liquid crystal molecules in a selected direction in a liquid crystal display cell. An alignment film whose film growth is oriented in the same direction is deposited on an electrode film of a liquid crystal cell. The alignment film is used to align the molecules of a liquid crystal material. The film growth sympathetically aligns the molecules of liquid crystals in the direction of the film growth. A liquid crystal display cell which has two such alignment films therein is used to form a polarizing liquid crystal display cell.
    Type: Grant
    Filed: August 7, 1978
    Date of Patent: August 28, 1979
    Assignee: NCR Corporation
    Inventor: John L. Janning
  • Patent number: 4156249
    Abstract: A semiconductor tunable capacitor is described. This tunable capacitor employs a plurality of metal-insulator-semiconductor (MIS) capacitive segments and each element has a first and a second value of capacitance. The solid state capacitor employs a plurality of tuning terminals and a single capacitor terminal. Tuning signals are applied to each of the tuning terminals for switching that capacitive segment into its high or low capacitive state. The capacitor terminal is capacitively connected to each capacitive segment and is employed for summing the individual values of capacitance into a total value of capacitance. An MNOS capacitor is shown as the preferred embodiment.
    Type: Grant
    Filed: June 5, 1978
    Date of Patent: May 22, 1979
    Assignee: NCR Corporation
    Inventor: Tuh-Kai Koo
  • Patent number: 4149904
    Abstract: A method of manufacturing a silicon gate MIS device using ion implantation and controlled ion scattering to provide concurrent formation and automatic alignment of the gate structure and adjacent impurity regions. In a preferred embodiment, the process is for the gate structure and source and drain of silicon gate FETs. The layered gate constituents--typically oxide and silicon--are formed on a semiconductor wafer. A photoresist mask which is larger than the desired gate size is formed on the silicon and the silicon is etched to the predetermined gate size beneath the overhanging mask. The photoresist mask is then used during ion implantation of the source and drain to establish the lateral surface boundaries within which ions are implanted. These lateral surface boundaries are selected so that as the ions are driven into the substrate to the desired junction depth of the source and drain by lateral scattering, the source and drain are aligned with the silicon gate electrode.
    Type: Grant
    Filed: October 21, 1977
    Date of Patent: April 17, 1979
    Assignee: NCR Corporation
    Inventor: Robert K. Jones
  • Patent number: 4145233
    Abstract: A method for making an FET comprising as many as three parallel channels having different threshold voltages. The two outer channels can have very low W/L ratios and resulting low drain-to-source currents. In one embodiment, the FET has a central enhancement channel flanked by low W/L ratio, low current, depletion channels. This FET is fabricated by (1) forming on the field oxide a photoresist mask having a relatively narrow aperture; (2) overetching the field oxide beneath the photoresist mask aperture to form a relatively wide aperture in the field oxide, leaving a photoresist overhang; (3) implanting the substrate through the relatively narrow photoresist mask aperture to provide an enhancement section of the channel region; (4) removing the photoresist mask; and (5) depletion implanting the substrate through the relatively wide field oxide aperture. The gate structure is formed over the combined enhancement and depletion channels and a source and a drain span the ends of the channels.
    Type: Grant
    Filed: May 26, 1978
    Date of Patent: March 20, 1979
    Assignee: NCR Corporation
    Inventors: Stephen A. Sefick, Robert K. Jones
  • Patent number: 4125427
    Abstract: An improvement of the prior art method of processing large scale integrated (LSI) semiconductors is disclosed, wherein an etching procedure, which was previously performed as the final processing step, is now done at an earlier stage to preclude damage to the surface of the wafer on which the active devices are formed. In the prior art method of fabricating an active device on a semiconductor wafer, an undesirable layer of field oxide manifests itself on the reverse side when the field oxide is grown on the obverse or principal side of the wafer. The prior processing philosophy was to allow the oxide layer to remain on the wafer until after the processing was completed and, as a final step, the undesired oxide coating was removed. This was done by carefully placing the wafer in a pool of etchant so that only the reverse side is etched.
    Type: Grant
    Filed: August 27, 1976
    Date of Patent: November 14, 1978
    Assignee: NCR Corporation
    Inventors: Peter C. Chen, John K. Stewart, Jr., Tuh-Kai Koo
  • Patent number: 4105930
    Abstract: A plasma discharge display device including at least one channel defined between opposing walls and containing an ionizable medium. Electrodes are employed for the application of potential differences whereby the medium will emit light proximate the electrodes. The electrodes include first and second AC electrodes on opposite wall surfaces, and third and fourth electrodes for developing a DC discharge in the vicinity of the first and second AC electrodes. The channel is divided into individual cells by means of insulating walls, and the DC discharge serves to prime individual cells, this discharge being developed at succeeding cells. The potential differences achieved by the AC electrodes across a given cell are selectively imparted whereby a primed cell can be caused to emit light. Thereafter, continued operation of the AC electrodes will maintain the light emission in the selected cells to provide a continuous display.
    Type: Grant
    Filed: July 19, 1976
    Date of Patent: August 8, 1978
    Assignee: NCR Corporation
    Inventor: William E. Coleman
  • Patent number: 4094008
    Abstract: A novel memory array is disclosed, the array utilizing a matrix of variable threshold insulated gate field effect transistor cells. The cells are comprised solely of a gate region, having nitride and oxide layers, and a source region with the output data sensed, at the source, as a change of source charge as distinguished from the prior art sensing of a change of low impedance source voltage. In operation, each cell functions as an alterable capacitor. A negative pulse applied to the gate selects the cell. Variations in stored charge at the nitride-oxide interface causes changes in the threshold voltage and effective capacitance of the cell. The source charge may then be sensed to read the stored data.
    Type: Grant
    Filed: June 18, 1976
    Date of Patent: June 6, 1978
    Assignee: NCR Corporation
    Inventors: George C. Lockwood, Nicholas E. Aneshansley
  • Patent number: 4075367
    Abstract: A method of providing improved adherence of photoresist to a silicon nitride layer on a semiconductor wafer by first preparing a heated solution of trichlorophenylsilane, immersing the nitride coated wafer in the trichlorophenylsilane solution, drying and baking the wafer prior to the application of the photoresist.
    Type: Grant
    Filed: March 18, 1976
    Date of Patent: February 21, 1978
    Assignee: NCR Corporation
    Inventor: Michael R. Gulett
  • Patent number: 4051408
    Abstract: A plasma charge display device having a channel containing an ionizable medium with the channel defining an endless length as in the case of a circular channel. At least one input electrode is located in a first position, and transfer electrodes extend away from the input electrode on opposite sides thereof completely along the length of the channel. Gas ionization results in the formation and shifting of light emitting areas in either direction relative to the position of the input electrode. The transfer electrode positions are related to the input electrode position in a manner such that the light emitting areas can be shifted through the position of the input electrode from one side to the other thereof.
    Type: Grant
    Filed: January 13, 1976
    Date of Patent: September 27, 1977
    Assignee: NCR Corporation
    Inventors: Herman Albertine, Jr., Donald G. Craycraft, William E. Coleman
  • Patent number: 4051409
    Abstract: A system for loading a plasma charge transfer device and for holding charges applied thereto. Input and transfer electrodes are positioned on opposing walls which define a channel confining an ionizable medium. The electrodes are arranged for the application of potential differences between adjacent electrodes whereby the charges may be shifted away from the input electrode to a desired location and in a desired pattern along the length of the device. The charges are then held at the desired location by applying potential differences in a fashion such that the charge is circulated between a set of at least four sequentially positioned transfer electrodes at the desired holding location.
    Type: Grant
    Filed: January 13, 1976
    Date of Patent: September 27, 1977
    Assignee: NCR Corporation
    Inventor: Donald Gregory Craycraft
  • Patent number: 4044280
    Abstract: An enclosure containing an ionizable gas has electrodes mounted in opposition on opposite faces of the enclosure. A first set of electrodes on one side of the enclosure are energized in sequence. A second set of electrodes on the opposite side of the enclosure form a multiple-element character matrix in which groups of elements are electrically commoned so that the number of electrodes, and respective leads thereto, in the second set is less than the number of elements of the matrix. The electrodes of the first set are mounted and shaped so that each is opposite a plurality of electrodes of the first set, and so that the same electrode of the second set is opposite several electrodes of the first set. Thus different portions of the same electrodes of the first set, representing different elements of the matrix, can be separately actuated during the different time periods of energization of the electrodes of the first set.
    Type: Grant
    Filed: October 30, 1975
    Date of Patent: August 23, 1977
    Assignee: NCR Corporation
    Inventor: Anton P. Shulski
  • Patent number: 4032373
    Abstract: A matrix array of semiconductor diodes formed in an epitaxial layer of a semiconductor wafer and being dielectrically isolated from each other by two orthogonal sets of parallel insulating oxide regions, one set extending completely through the epitaxial layer and the other set extending only partially through the epitaxial layer. A preferred method of forming the matrix array is also disclosed.
    Type: Grant
    Filed: October 1, 1975
    Date of Patent: June 28, 1977
    Assignee: NCR Corporation
    Inventor: Tuh-Kai Koo
  • Patent number: 4027197
    Abstract: A plasma glow tube for displaying a bar of selectable length comprises an insulating enclosure filled with an ionizable gas. The enclosure may have flat opposing sides, the inside walls of which have conductive electrodes (preferably transparent) deposited thereover in a staggered pattern such that each electrode, except the end ones, is positioned between and equidistant from two opposing electrodes. The electrodes, except for the first and last electrodes which are DC coupled to the gas, are all covered with an insulating layer so that they are insulated from the gas. A potential difference, preferably in the form of a pulse, is applied between first and second end electrodes to ionize the gas therebetween and leave an inside wall charge adjacent said second electrode. A pulse is applied between the charged electrode and the next succeeding, opposite (third) electrode to ionize the gas therebetween and leave a charge on the third electrode, and so on.
    Type: Grant
    Filed: October 8, 1975
    Date of Patent: May 31, 1977
    Assignee: NCR Corporation
    Inventor: William E. Coleman