Abstract: Bioavailability of lead and other heavy metals in the environment may be reduced by addition of microorganisms which sequester lead from the environment in the presence of phosphate. The microorganisms are highly mobile and are, therefore, capable of scavenging a material for lead, which they then sequester. The method basically consists of reducing bioavailability of lead in the environment by addition of Pseudomonas aeruginosa strain CHL004 (ATCC 55937) to said environment in the presence of phosphate which contains at least stoichiometric equivalent amounts of phosphate to lead.

Abstract: A method and apparatus for performing operations at nodes in a distributed network of interconnected nodes wherein a two dimensional array is arranged with each of the nodes represented by a single row heading and a single column heading. The intersections of row and column headings at which operations are to be performed may be provided with a token indicative of this condition. The token may further be associated with operation parameters defining the performance of the operations at the two nodes represented by the intersecting row and column headings.

Abstract: The invention relates to a memory device comprising a set of word decoders W, a set of wordline drivers WL, a plurality of switches S to connect a subset of the wordline drivers to the set of word decoders and storage means 5 for the storage of information indicative of a defective wordline. The wordline drivers include a predefined subset of wordline drivers which are to be used when none of the wordlines are defective and a plurality of second subsets of wordline drivers which are to be used when one of the wordlines is defective. The memory device further includes logic means 4 for logically and permanently assigning one of the subsets to the set of word decoders in response to the information stored in the storage means, by controlling the switches S to connect one of the second subsets of wordline drivers to the set of word decoders.

Abstract: A method and apparatus for sequencing the operation of electronic circuits based upon the level of the voltage provided by an external power supply. One or more power supply sequencer circuits may be interposed between an external power supply and one or more electronic circuits. The power supply sequencer circuits comprise a transistor having its high current node coupled to an external power supply, its controlling node coupled to a voltage sequencing means such as a diode and a resistor, wherein the resistor is in turn coupled to the external power supply and the diode is coupled to the ground potential. The transistor has its controlled high current node coupled through a power input node to the power input for the electronic circuit to condition the voltage received thereby. The power input node is in turn coupled through a second resistor to ground potential.

Abstract: A virtual two-port memory structure with fast write-thru operation is proposed. The virtual two-port memory structure employs a single-port memory cell (200). Means for comparing (260) compare a read address AR with a write address AW and means (270) for writing data from the data input terminal (250) into the cell (200) are bypassing said data to the data output terminal (280) as well, such that a write-thru operation is enabled if the read address AR matches the write address AW. The data just written into the cell are immediately available as read data within the same cycle. The multiplex unit used in prior art solutions is no longer necessary, the delay caused by this device is omitted and the advantages of the virtual two-port cell requiring less chip space are maintained.