Abstract: An asymmetrical ESD protection device and a method of production thereof are provided. A source region and a drain region are formed in a substrate. A gate is formed over the substrate between the drain and source regions. A compensating implant is formed under the source region. The compensating may either be an additional implant or an existing BR resistor well. The compensating implant extends deeper into the substrate than the drain region.

Abstract: An SOI structure with a dual thickness buried insulating layer and method of forming the same is provided. A first substrate has raised portions each with a planar top surface. A dielectric layer covers the first substrate and its raised portions. The dielectric layer has a planar top surface. A second substrate layer is formed on the planar top surface of the dielectric layer. Semiconductor elements may be formed in the second substrate layer. The semiconductor elements pertain to core circuit elements, peripheral circuits, and electrostatic discharge (EDS) circuits.

Abstract: A system and method for decoupling graphics operations from a host processor to improve the efficiency of graphics rendering and free the host processor for other essential tasks. A processing system includes a host processor, a memory, a display list processor (DLP), graphics accelerators and display hardware. The host processor builds display lists generated by graphics applications and stores the display lists in the memory. The display lists include hardware function directives and control directives. The DLP accesses the memory to process the display lists, issuing the hardware function directives to the accelerators to generate display data.

Abstract: In an electronic device with an active region on top of and isolated from an substrate, a first material region is defined on top of and/or adjacent to and electrically isolated from the active region and a second material region is attached to a surface of the first material region to form an interface defining a Peltier cooling junction therebetween. A current source connected in series to the first and the second material regions produces a cooling effect at the Peltier cooling junction.

Abstract: A method for dry etching metals that form low volatility chlordes, in which Z-Cl reaction products are controllably introduced into a conventional Cl-based plasma independent of the workpiece. The Z-Cl products (e.g., AlCl.sub.3, GaCl.sub.3, etc.) are metal chlorides that have both electron acceptor and chloride donor properties. Thus, metals M (e.g., cobalt, copper and nickel) that usually produce low volatility chlorides can be controllably complexed to form high volatility Z.sub.x Cl.sub.y M.sub.z reaction products.

Abstract: By hydrolyzing an organoalkoysilane monomer at high concentration in solution to form a silanol, allowing the silanol to age to produce a low molecular weight oligomer, spin-applying the oligomer onto a substrate to form a discrete film of highly associated cyclic oligomer thereon, heat treating the oligomer film to form a modified ladder-type silsesquioxane condensation polymer, and then oxidizing the silsesquioxane in an O.sub.2 RIE, an organoglass is formed which presents novel etch properties. The organoglass can be used as an etch-stop layer in a passivation process.

Abstract: A method of improving the adhesion between a synthetic substrate and metallized layers deposited thereon. A glass resin layer is spin-coated onto an epoxide substrate. The glass layer is covered by a photoresist layer which is roughened by reactive ion etching. The roughened contour of the photoresist layer is transferred via reactive ion etching to form a perforation pattern in the glass layer. The substrate is then etched vertically and horizontally to produce recesses in the substrate having overhanging walls. A thin copper layer is sputtered onto the substrate and copper conductors are sputtered onto the thin copper layer, the copper layers filling the recesses. The recesses and overhangs form mortices in the substrate, and the copper layers within the recess form tenons which fittingly engage with the mortices to produce adhesion between the substrate and the metallized layers in the order of 1000 n/m.

Abstract: An FET double boosted clock driver for producing a clock signal having an amplitude greater than the drain supply voltage. The clock output of a second clock driver is capacitively coupled to the clock output of a first clock driver. The second clock driver boosts the voltage on the source of an enhancement mode (output) FET of the first clock driver. The output FET has its gate connected to a bootstrapped node and its drain connected to a drain voltage source (VDD). A depletion mode FET forms a feedback path between the source of the output node FET and the bootstrapped node. When the bootstrapped node is bootstrapped to VDD+VT, the output FET precharges the clock output to VDD. When the potential of the clock output approaches VDD, the depletion mode FET discharges the bootstrapped node to an input clock.

Abstract: Supplying of foils to be applied to both sides of a workpiece. Opposing feeding drums have identical exchangeable segments whose circumferential lengths correspond to the length of the respective foil segment lamina, and whose segment angle sums are less than 360.degree.. In order to affix a leading edge of the foil to the leading edge of the workpiece, the foil is cut at the back end of the segment, and a first segment (on whose circumference the foil segment lamina is fixed) is moved toward the workpiece. After the foil adheres to the board, the drum segment is withdrawn. During the course of further movement of the workpiece, the foil segment is stripped off the segment by use of a laminating roller and a vacuum shoe. The drum is then rotated so that for the next workpiece to be laminated, the second segment will become operative as a supply element for the foil.