Abstract: A sample holder and auxiliary apparatus are provided to position and hold a sample in the sample holder. A method of positioning and holding a sample in the sample holder is also provided. The sample holder preferably includes a holder body having a sample holding portion arranged therein. An opening in the sample holding portion is configured to receive a sample therein. An elastic member is configured to supply a holding force to hold the sample in the opening. The auxiliary apparatus preferably includes one or more holder supports configured to support a sample holder. The auxiliary apparatus is configured to receive the sample holder and force a sample holding member of the sample holder into a rearward position to permit the sample holder to receive a sample into an opening thereof.

Abstract: A method for manufacturing a chip scale package (CSP) including a semiconductor chip and conductive bumps is disclosed. In the present invention, a flexible substrate is provided with a conductive pattern formed thereon. The substrate has a top surface and a bottom surface. Then, a first photosensitive resin pattern is formed over the top surface of the substrate. Next, the first photosensitive resin pattern is cured. Subsequently, a second photosensitive resin pattern is formed over the cured first photosensitive resin pattern. The second photosensitive resin pattern includes a slit comprising a bottom of the first photosensitive resin pattern and side walls of the second photosensitive resin pattern. With the present invention, the problem of burning of neighboring patterns as well as the problem of the overflow of the encapsulant can be overcome.

Abstract: A method for forming a metal interconnection filing a contact hole or a groove having a high aspect ratio. An interdielectric layer pattern having a recessed region corresponding to the contact hole or the groove is formed on a semiconductor substrate, and a barrier metal layer is formed on the entire surface of the resultant structure where the interdielectric layer pattern is formed. An anti-nucleation layer is selectively formed only on the non-recessed region of the barrier metal layer, thereby exposing the barrier metal layer formed on the sidewalls and the bottom of the recessed region. Subsequently, a metal plug is selectively formed in the recessed region, surrounded by the barrier metal layer, thereby forming a metal interconnection for completely filling the contact hole or the groove having a high aspect ratio.