Abstract: A machine-controlled method can include determining an extended interval quality of service (QoS) specification for a batch job and determining a remaining data center resource requirement for the batch job based on the extended interval QoS specification. The machine-controlled method can also include determining an immediate QoS specification for the batch job based on the remaining data center resource requirement.

Abstract: An ion beam apparatus includes a plasma chamber with a grid assembly installed at one end of the plasma chamber and a plasma sheath controller disposed between the plasma chamber and the grid assembly. The grid assembly includes first ion extraction apertures. The plasma sheath controller includes second ion extraction apertures smaller than the first ion extraction apertures. When the plasma sheath controller is used in this configuration, the surface of the plasma takes on a more planar configuration adjacent the controller so that ions, extracted from the plasma in a perpendicular direction to the plasma surface, pass cleanly through the apertures of the grid assembly rather than collide with the sidewalls of the grid assembly apertures. A semiconductor manufacturing apparatus and method for forming an ion beam are also provided.

Abstract: A fuse circuit may include a fuse cut detection unit to output state information indicating whether or not a fuse is cut during a fuse cut detection time period, a maintenance and output unit to maintain the state information and output a fuse state information signal, and a connection/disconnection unit to connect the fuse cut detection unit to the maintenance and output unit during the fuse cut detection time period and disconnect the fuse cut detection unit from the maintenance and output unit after the fuse cut detection time period. A fuse circuit may recognize an indefinite voltage at a detection node caused by a leakage path through a fuse as a predetermined fuse state.

Abstract: Disclosed is a dynamic random access memory (DRAM) device having word line low voltage supply lines for driving word lines in a mesh structure. The DRAM device includes a plurality of cell arrays each of which is formed of memory cells coupled to word lines and bit lines in a matrix. The memory device further includes regions of sense amplifiers disposed between the cell arrays arranged along the row direction, regions of word line drivers disposed between the cell arrays arranged along the column direction, conjunction regions disposed at positions adjacent to the regions of the sense amplifiers and word line drivers, and a plurality of word line low voltage supply lines disposed on the conjunction regions. The word line low voltage supply lines are electrically interconnected for each other at least on the conjunction regions. According to the layout arrangement, loadings of the word line low voltage supply lines are almost equally distributed, and thereby word line low noise are decreased.