Abstract: There is provided a method of fabricating a local SONOS type gate structure and a method of fabricating a nonvolatile memory cell having the same. The method includes forming a gate dielectric layer on a semiconductor substrate. A gate pattern, including a gate electrode and a hard mask layer pattern which are sequentially stacked, is formed on the gate dielectric layer. Then, a recess is formed on the boundary of the gate pattern and the gate dielectric layer. The recess is formed on one side wall of the gate pattern, and is prevented from forming on the other side wall of the gate pattern. A tunnel layer and a trapping dielectric layer are sequentially formed on substantially the entire surface of the semiconductor substrate having the recess formed thereon to fill the recess. At least a portion of the trapping dielectric layer is formed inside the recess.

Abstract: The present invention discloses an apparatus for transporting wafers. The apparatus includes a tray having a sloped portion on which a wafer having a sidewall can be mounted, a plurality of guides that disposed about the tray, and a plurality of sensors for detecting the position of the sidewall of the wafer with respect to the tray on which it is mounted by sensing the position of the sidewall. The present invention also discloses an apparatus for polishing wafers having the apparatus for transporting wafers comprising the circular tray and a plurality of guides and a plurality of sensors above-mentioned.

Abstract: This disclosure provides cells of nonvolatile memory devices with floating gates and methods for fabricating the same. The cell of the nonvolatile memory device includes device isolation layers in parallel with each other on a predetermined region of a semiconductor substrate that define a plurality of active regions. Each device isolation layer has sidewalls that project over the semiconductor substrate. A plurality of word lines crosses over the device isolation layers. A tunnel oxide layer, a floating gate, a gate interlayer dielectric layer, and a control gate electrode are sequentially stacked between each active region and each word line. The floating gate and the control gate electrode have sidewalls that are self-aligned to the adjacent device isolation layers.

Abstract: A three-dimensional, multi-chip package with chip selection pads formed at the chip-level and a manufacturing method thereof are provided. The three-dimensional, multi-chip package is formed by stacking a number (N) of semiconductor integrated circuit chips. Each chip comprises an integrated circuit die, a chip selection terminal, (N−1) chip selection pads, an insulation layer, (N−1) metal wirings, upper connection terminals, lower connection terminals, and trench wirings. The chip selection terminal of each chip is separated from the chip selection of the other chips by the chip selection pads formed at the chip-level.

Abstract: A flash memory device with an improved erase algorithm for erasing a plurality of memory cells that are arranged in intersections of wordlines and bitlines, respectively, includes an array of the memory cells. In the erase algorithm, all memory cells of the sector are erased at the same time. A pass/fail check & control logic then checks whether the memory cells are overerased. When one of a group of the erased memory cells is overerased, soft-program voltages are applied to the overerased memory cells such that the over-erased memory cells become soft-programmed. After boosting one of the soft-program voltages, the operations of checking, soft-programming, and boosting are carried out repeatedly, until a threshold voltage of the overerased memory cell moves within a target threshold voltage range of the erased memory cell. Therefore, overerasing is cured based upon program characteristics, without overcuring.

Abstract: A trench isolation method of a semiconductor integrated circuit is provided. In the trench isolation method, a mask pattern which defines a first opening and a second opening wider than the first opening is formed on a semiconductor substrate. A first spacer for filling the first opening and a second spacer are formed at the sidewalls of the second opening. A sacrificial material layer pattern having an etching rate substantially equal to that of the semiconductor substrate is formed in the second opening surrounded by the second spacer. The semiconductor substrate under the first and second spacers is exposed by selectively removing the first and second spacers. A deep trench region and a shallow trench region are formed in the exposed semiconductor substrate and under the sacrificial material layer, respectively, by etching the exposed semiconductor substrate and the sacrificial material layer pattern. An isolation layer filling the deep trench region and the shallow trench region is formed.

Abstract: A reference circuit, which is applied to a ferroelectric random access memory device, includes a polarization state detection circuit having dummy cells with ferroelectric capacitors. The detection circuit checks polarization states of the ferroelectric capacitor in the dummy cells using dumping voltages of different levels, and generates pass/fail signals as a check result. The generated pass/fail signals are decoded, using themselves as selection information for selecting one of reference voltages, of different levels, which are generated from a reference voltage generation circuit. Thus, it is possible to generate an optimal reference voltage, which senses a ferroelectric capacitor polarization state that is changed with time.