Abstract: An embodiment of the instant invention is a method of fabricating an electrical device having a structure overlying a semiconductor substrate which is planarized using chemical mechanical planarization, the method comprising the steps of: forming a layer of material over the semiconductor wafer; polishing the layer of material by subjecting it to a polishing pad and a slurry which includes peroxygen; and wherein the slurry additionally includes a stabilizing agent which retards the decomposition of the peroxygen in the slurry. Preferably, the stabilizing agent is comprised of: pyrophosphoric acids, polyphosphonic acids, polyphosphoric acids, Ethylenediamine Tetraacetic acid, a salt of the pyrophosphoric acids, a salt of the polyphosphonic acids, a salt of the polyphosphoric acids, a salt of the Ethylenediamine Tetraacetic acid and any combination thereof. In addition, the stabilizing agent may be comprised of: sodium pyrophosphate decahydrate, sodium pyrophosphate decahydrate, and/or 8-hydroxyquinoline.

Abstract: A new liner structure and method to incorporate this liner into process flows in order to lower the processing temperature of aluminum extrusion or reflow cavity filling. The structures produced by this innovative method are particularly useful for advanced sub-quarter micron multi-level interconnect applications.

Abstract: An embodiment of the instant invention is a method of forming a semiconductor device situated over a semiconductor substrate, the method comprising the steps of: forming a layer of suboxide material (layer 206 of FIG. 2a) over the substrate (substrate 202 of FIGS. 2a-2c), the suboxide material comprised of a material selected from the group consisting of: HfSiOx, ZrSiOx, LaSiOx, YSiOx, ScSiOx, and CeSiOx; and forming a structure (layer 210 of FIG. 2c) on the layer of suboxide material. In an alternative embodiment, semiconductor device is a transistor where and the structure formed on the layer of suboxide material is a gate electrode (preferably comprised of: polycrystalline silicon, tungsten, titanium, tungsten nitride, titanium nitride, platinum, aluminum, and any combination thereof).

Abstract: An embodiment of the instant invention is a method of fabricating an electronic device formed on a semiconductor wafer, the method comprising the steps of: forming a conductive structure over the substrate, the conductive structure comprised of an oxygen-sensitive conductor; forming a layer of dielectric material over the conductive structure (step 306 of FIG. 1); forming a photoresist layer over the layer of the dielectric material (step 308 of FIG. 1); patterning the layer of the dielectric material (step 308); removing the photoresist layer after patterning the layer of the dielectric material (step 312 of FIG. 1); and subjecting the semiconductor wafer to a plasma which incorporates the combination of hydrogen or deuterium and a fluorine-containing mixture which is comprised of a gas selected from the group consisting of: CF4, C2F6, CHF3, CFH3 and other fluorine-containing hydrocarbon (step 313 of FIG. 1).

Abstract: The improved rinse tank includes an external shell and an internal shell. For one embodiment, the external shell preferably defines a five sided open-top tank with a top open to the atmosphere. The internal shell is preferably disposed within the external shell and has a configuration that will accommodate at least two semiconductor wafer boats filled with six inch semiconductor wafers. The external shell is preferably sized large enough to completely immerse the wafer boat and wafers in water when the rinse tank is filled. A chamber may be formed between the external shell and the internal shell within the lower portion of the rinse tank. Two or more deionized water inlets may be provided at the bottom of the rinse tank at opposite corners. Three or more compressed air nozzles may also be provided at the lower portion of the rinse tank. Multiple deionized water jet ports are provided at the internal shell.

Abstract: A method of filtering a bath (1,31) having a liquid containing particles of varying sizes therein and the recirculation and filtering system. The method and system require providing a recirculation route from the bath outflow and returning to the bath inflow. The route includes a first path communicating with the bath outflow and having serially a first controllable valve (5,9) and a filter having a relatively large pore size. The route also includes a second path communicating with the bath outflow and having serially a second controllable valve (11,15) and a filter having a relatively small pore size. There is a return path from each filter to the bath inflow. The return path from each filter can be a separate path or the paths can be connected at the output end before returning to the bath.

Abstract: An FET and DRAM using a plurality of such FETs wherein each transistor has a body region (27) of a first conductivity type including a relatively high VT region (p) and a relatively low VT region (p−), the high VT region disposed contiguous with the low VT region. A pair of source/drain regions (23, 25) of opposite conductivity type are disposed on a pair of opposing sides of the low VT region. The transistor includes a gate oxide (31) over the body region and a gate electrode (29) over the gate oxide and spaced from the body region. The body region is p-doped or n-doped with the high VT region more heavily doped than the remainder of the body. In a further embodiment, the FET includes a body region of a first conductivity type which includes a relatively low VT region and a first pair of relatively high VT regions on a first pair of opposing sides of the body. A pair of source/drain regions of opposite conductivity type are disposed on a second pair of opposing sides of each of the low VT region.

Abstract: A structure and method to direct the via 270 etch to the top of the interconnect 210, by using a sidewall layer 240, preferably. TiN, and thus preventing the etching down the side of the interconnect 210 and exposure of materials residing between the interconnects 210.

Abstract: A probe (10) has a main body (12), an input side (14) and an output side (16). The main body (12) has a cavity (17) to receive an insulator (18). The insulator (18) has a current slit (22) and a voltage slit (24) aligned with a first aperture (30a) and a second aperture (30b). An inner conductor extends through the insulator (18) from the input side (14) to the output side (42) of the main body (12). A current sensor (40) inserts into the first aperture (30a) and the current slit (22). A voltage sensor (50) inserts into the second aperture (30b) and the voltage slit (24). A radio frequency signal on a transmission line having a same impedance as the probe (10) enters the inner conductor (20) at the input side (14), induces a current onto the current sensor (40) and a voltage onto the voltage sensor (50). The induced current and voltage can be measured to monitor the characteristics of the transmission line.

Abstract: An embodiment of the instant invention is an optical illumination system for illuminating the mask of an exposure apparatus for transferring the image of the pattern on the mask onto the semiconductor wafer, the optical illumination system comprising: illumination means (illumination means 45 of FIG. 3) comprised of a plurality of light sources for emitting light beams along beam paths; and a lens system (lenses 55 and 57 of FIG. 3) for focusing the light beams to the wafer, the lens system comprising at least one lens element positioned in the beams paths. Preferably, the light sources are individually addressable point like sources, and the optical illumination system further comprising a light control means for operating each of the light sources independently of the others.

Abstract: An embodiment of the instant invention is a method of fabricating an electronic device over a semiconductor substrate, the method comprising the steps of: forming a doped polycrystalline silicon layer insulatively disposed over the semiconductor substrate; and subjecting the doped polycrystalline silicon layer to a temperature of around 700 to 1100 C. in an oxidizing ambient for a period of around 5 to 120 seconds. Preferably, the oxidizing ambient is comprised of: O2,O3, NO, N2O, H2O, and any combination thereof. The temperature is, preferably, around 950 to 1050 C. (more preferably around 1000 C.). The step of subjecting the doped polycrystalline silicon layer to a temperature of around 700 to 1100 C. in an oxidizing ambient for a period of around 5 to 120 seconds, preferably, forms an oxide layer on the polycrystalline silicon layer, which has a thickness which is, preferably, greater than the thickness of a native oxide layer.

Abstract: An embodiment of the instant invention is a method of making a transistor having a silicided gate structure insulatively disposed over a semiconductor substrate which lies in an x-y plane, the method comprising the steps of: forming a semiconductive structure insulatively disposed over the semiconductor substrate (step 302 of FIG. 3); amorphizing a portion of the conductive structure by introducing an amorphizing substance into the semiconductive structure at an angle, theta, which is greater than seven degrees from a z-axis which is normal to the semiconductor substrate (step 310 of FIG. 3); forming a metal layer on the conductive structure (step 312 of FIG. 3); and wherein the metal layer interacts with the semiconductive structure in the amorphized portion of the conductive structure so as to form a lower resistivity silicide on the conductive structure (step 314 of FIG. 3).

Abstract: An improved microlithographic imaging system (100) is disclosed. The system comprises a filter (183) substantially aligned with a first image plane, adjacent to an aperture (185). The filter is formed in response to an image projected by a light source (110) through a reticle (160) onto the first image plane. The improved microlithographic imaging system has higher resolution and depth of focus than prior art imaging systems, due to the additional filtering performed by the filter (183). A filter in accordance with the invention can be fabricated easily and inexpensively, using conventional microlithography techniques. A filter in accordance with the invention can also be used to detect or correct flaws in the reticle (160).

Abstract: An integrated circuit fabrication method for filling a high-aspect-ratio via with a metallization layer wherein there is provided a dielectric layer having a via therein. A wetting layer is deposited over the dielectric layer and within the via and the via sidewalls, the wetting layer being of a material which lowers the melting temperature of the metallization when combined with the metallization. The metallization layer is deposited over the wetting layer and the via but not completely filling the via with the metallization. The wetting agent with metallization thereon are heated to a temperature below the melting temperature of the metallization, the temperature being sufficient to cause the wetting layer to combine with the metallization, lower the melting temperature of the metallization to the temperature or below the heating temperature to cause the metallization to flow and fill the via.

Abstract: An integrated circuit fabrication process in which residual fluorine contamination on metal surfaces after ashing is removed by exposure to an NH.sub.3 /O.sub.2 plasma.

Abstract: A process for producing conformal and stable TiN+Al films, which provides flexibility in selecting the chemical composition and layering. In this new process, porous TiCN is first deposited, and then Al is incorporated by exposing the porous film to CVD aluminum conditions at low temperatures.

Abstract: An embodiment of the instant invention is a method of substantially isolating an electrical device over a semiconductor substrate from a structure which collects charge, the method comprising the steps of: forming an insulating layer (layer 304) on the substrate; forming a conductive layer (layer 306) on the insulating layer; incorporating at least one element (element 310) into portions of the conductive layer so as to render that portion the conductive layer more resistive; and wherein the portion of the conductive layer which has been rendered more resistive (region 312) is rendered conductive after one or more charging events by subjecting the portion of the conductive layer to an elevated temperature. Preferably, the element is comprised of an element selected from the group comprised of: As, P, N, Ar, Si, H, B, Ge, C, Sb, F, Cl, O, any noble element, and any combination thereof and their isotopes.

Abstract: A system and process for analyzing the plasma discharge for various frequency components that can be correlated to wafer, chamber or equipment conditions. This system and process monitors (step 210), by using optical or electrical signals from the plasma, the low frequency plasma variations (step 220) generated during the wafer manufacturing process. For example, in endpoint detection applications, the amplitude variations of the plasma glow at a selected audio frequency, chosen for sensitivity to the etched material, is used to generate the endpoint signal (step 230). This endpoint signal has a potential response time equal to one cycle of the selected frequency plus minimal filtering due to noise reduction. To extract the vital parameters from the plasma glow, DSPs for frequency analysis or simple frequency filtering methods can be used.

Abstract: A method for making a memory cell (10) in a process in which both an n-channel MOS transistors (12) and a p-channel transistor (44) are formed in a semiconductor substrate (30) is presented. The method includes implanting an impurity (40) into a region of the substrate (30) to form a part of a depletion NMOS memory capacitor (21) to be associated with the n-channel MOS memory transistor (12). The implant is performed concurrently with a patterned implant with the same impurity to adjust the threshold and punch-through of the p-channel transistor (44).

Abstract: An embodiment of the instant invention is a scanning-probe microscope for measuring the topography of a surface of a sample, the scanning-probe microscope comprising: an XYZ piezo drive (piezo drive 1); a quartz tuning-fork oscillator (fork 2) having a first electrode (electrode 3 or 4) and a second electrode (electrode 3 or 4), wherein the quartz tuning-fork oscillator is attached to the XYZ piezo drive, and wherein the quartz tuning-fork oscillator is oriented such that the tines of the quartz tuning-fork oscillator each lie in the XY plane and their fundamental mode of oscillation vibrates the ends of the tines in the Z direction; a probe tip (probe tip 6) affixed to one of the tines, the probe tip comes to a point in the Z direction and directed away from the XYZ piezo drive; a signal source (source 7) to provide a drive signal to drive the first electrode at a mechanical resonant frequency of the quartz tuning-fork oscillator; a current-to-voltage amplifier (preamp 8) to monitor the electrical current fl