Abstract: An optical line terminal (OLT) determines when an optical network terminal (ONT) has become a rogue ONT, and then identifies the rogue ONT so that service can be restored. The OLT identifies the rogue ONT by comparing the received power levels with the levels that would be expected during normal operation.

Abstract: A method of forming an actuator and a relay using a micro-electromechanical (MEMS)-based process is disclosed. The method first forms the lower sections of a square copper coil, and then forms a magnetic core member. The magnetic core member, which lies directly over the lower coil sections, is electrically isolated from the lower coil sections. The method next forms the side and upper sections of the coil, followed by the formation of an overlying cantilevered magnetic flexible member. Switch electrodes, which are separated by a switch gap, can be formed on the magnetic core member and the magnetic flexible member, and closed and opened in response to the electromagnetic field that arises in response to a current in the coil.

Abstract: A silicon-based light emitting structure is formed as a high density array of light-emitting p-n junctions that substantially increases the intensity of the light emitted in a planar region. The p-n junctions are formed using standard CMOS processing methods, and emit light in response to applied voltages that generate avalanche breakdown and an avalanche current.

Abstract: An optical switch is implemented with one or more cantilevered optical channels, which are formed in a flexible waveguide structure, and an actuator which is connected to the cantilevered optical channels, to position the cantilevered optical channels to direct an optical signal along one of a number of optical pathways.

Abstract: Access to a bus is granted to one of a number of requesting communication circuits that each submitted a bus control request during a request period of an arbitration period in response to the entries in a priority table. If a requesting communication circuit has an identity and priority that match the identity and priority of a communication circuit stored in a row of the priority table that corresponds with the arbitration period, access to the bus is granted to the requesting communication circuit.

Abstract: A vertical MOS transistor has a source region, a channel region, and a drain region that are vertically stacked, and a trench that extends from the top surface of the drain region through the drain region, the channel region, and partially into the source region. The vertical MOS transistor also has an insulation layer that lines the trench, and a conductive gate region that contacts the insulation layer to fill up the trench.

Abstract: A ballasting region is placed between the base region and the collector contact of a bipolar junction transistor to relocate a hot spot away from the collector contact of the transistor. Relocating the hot spot away from the collector contact prevents the collector contact from melting during an electrostatic discharge (ESD) pulse.

Abstract: A zero crossing detector employs carry save adders combined with fully pipelined logic to provide two-bit, three-bit or four-bit zero crossing detection. The detector offers the advantages of very high operating speed, very low power dissipation, low adder cell count and reduced chip area.

Abstract: A driver circuit limits the magnitude of the initial wave front launched onto a transmission line to a voltage that is approximately one-half of the supply voltage. Thus, immediately after the initial wave front is reflected from an open circuit receiver, a voltage at the receiver is approximately equal to the supply voltage when a rising voltage is launched, and ground when a falling voltage is launched.

Abstract: A chip is initialized by a power-on reset circuit, after a turned-on power supply has reached a voltage level sufficient for normal chip operation. Logic gating is used to provide a glitch-free trigger signal that prevents erroneous chip re-initialization due to VDD glitches, and to provide a crystal warm-up delay that can be quickly tested without the use of dedicated I/O pins.

Abstract: When a high-voltage, such as from an ESD pulse, is placed across a silicon controlled rectifier, which includes an NPN transistor and a PNP transistor that is connected to the NPN transistor, the likelihood of punch through occurring between two regions of the rectifier is substantially reduced by forming the collector of the NPN transistor between the emitter and collector of the PNP transistor.

Abstract: A wafer is formed with metal traces that extend a distance across the wafer on opposite sides of a saw street. The resistances of the metal traces, which can each be formed from one or more layers of metal, are measured before the saw street is cut. During and after the saw street is cut, the resistances of the metal traces are again measured, even continuously. The pre-cut, during-cut, and post-cut resistances are compared to determine if the wafer has been cut without damage to the wafer due to misalignment or a worn cutting device.

Abstract: A three-terminal snapback device is utilized with a control circuit to provide a low snapback voltage that is protected from non-ESD voltage spikes and ripples. In response to a fast edge, the control circuit lowers the snapback voltage, unless a status signal indicates that normal operating voltages are present, and raises the snapback voltage a predefined time later. If the fast edge represents an ESD pulse, SCR operation is initiated at the lowered snapback voltage. If the fast edge represents a power on sequence, the maximum voltage is less than the momentarily lowered snapback voltage and therefore insufficient to initiate SCR operation. Further, once normal operating voltages are present, the control circuit continuously maintains the raised snapback voltage so that a non-ESD voltage spike or ripple can not improperly turn on the snapback device.

Abstract: Resistance and capacitance are added to a prototype die to fix or identify performance issues with the integrated circuit formed in the die by forming a thin piece of silicon on the top surface of the die. For resistance, vias are formed to regions on the metal traces and to opposite ends of the piece of silicon using a FIB system. For capacitance, a dielectric is formed on the piece of silicon, and a layer of metal is formed on the dielectric. Vias are formed to regions on the metal traces, to the piece of silicon, and to the layer of metal using the FIB system.

Abstract: The drains of the PMOS transistor and the NMOS transistor of a driver are separated and connected to two spaced-apart pins. The spaced-apart pins provide ESD protection to the NMOS transistor, which can be turned on during an ESD event by voltages that propagate through the PMOS transistor during the ESD event.

Abstract: A method performs quality control testing on the objects in a set of objects to obtain a level of quality. The method identifies a number of objects that satisfy the static testing limits, determines statistical measures from the number of objects, determines a dynamic range of values from the statistical measures, and then identifies the objects that satisfy the dynamic range of values.

Abstract: The power required to search a content addressable memory (CAM) is substantially reduced by forming the CAM to have a number of CAM banks with a corresponding number of power switches that control power to the CAM banks, and then controlling the power to search the CAM banks one at a time.

Abstract: Thermal hot spots in the substrate of a semiconductor die, and the required surface area of the semiconductor die, are substantially reduced by forming thermal or thermal and electrical pipes in the substrate that extend from a bottom surface of the substrate to a point near the top surface of the substrate.

Abstract: Various semiconductor devices can be formed at the end of a common fabrication process, thereby significantly improving manufacturing flexibility, by selectively wiring bonding different CMOS circuits to different MEMS, which are formed on the same semiconductor die. A semiconductor device that has a number of CMOS circuits and a number of MEMS is formed on the same semiconductor wafer in adjacent regions on the wafer, and then diced such that the CMOS circuits and the MEMS are formed on the same die. After dicing, different CMOS circuits and different MEMS can be selectively connected during the wire bonding step to form the different semiconductor devices.

Abstract: The RF impedance of a metal trace at gigahertz frequencies is reduced by forming the metal trace to have a base region and a number of fingers that extend away from the base region. When formed to have a number of loops, the metal trace forms an inductor with an increased Q.