Abstract: A method to read and write at least one static memory cell is provided, said cell comprising a cross-coupled inverter pair and two pass-devices wherein said method is characterized in that during read only one of the two pass-devices is selected, while for write both pass-devices are selected. Furthermore, a circuit to read and write at least one static memory cell is described, said cell comprising a cross-coupled inverter pair and two pass-devices. Said circuit is characterized in that for each pass-device of the cell an individual wordline is connected with a gate of the particular pass-device, wherein both wordlines are selected for write and a single wordline is selected for read.

Abstract: A content addressable memory (CAM) system is disclosed including a dual mode cycle boundary latch (CBL). The CBL includes a master latch coupled to a slave latch. The CBL operates in a high speed functional mode and a lower speed test mode. In the high speed functional mode, input data bypasses the master latch and transports directly to the CBL output via the slave latch. The CBL effectively removes the master latch from the circuit in the high speed functional mode. However, in the lower speed test mode, input test data travels via both the master and slave latches to the CBL output.

Abstract: A location-based service includes detecting the relative motion of an on-site resource, such as a shopping cart, in addition to detecting the absolute position of the on-site resource, and displaying information on the on-site resource. The displayed information is based upon the detected relative motion and the detected absolute position. The relative motion is tracked and a position on a floor plan is deduced. This deduced position is adjusted, for example, synchronized or reset, as a function of and in response to the detected absolute position.

Abstract: A CAM system is disclosed in which compare data, for example an address translation request, is provided as input search data to a search line generator. The search line generator presents search line input data, through a buffer, to CAM and RAM array systems that include dynamically precharged and evaluated memory cells. Timing sequences in the CAM system are controlled by a series of individually triggered one shot pulse generators. The one shot pulse generators control the timing of CAM system activities, for example the precharge of CAM subsystems, so that these activities are staggered in time. This timing approach improves power consumption and evaluation time within the CAM system. By distributing precharging activities in time throughout the CAM cycle, current peaking during the CAM cycle is reduced. The CAM system latches results in an output latch that is controlled by a one shot pulse generator.

Abstract: A portable information processing apparatus in provided with a magnetic disk device switchable to a state providing increased resistance to physical shock upon prediction that such a shock is likely. Under predetermined conditions, a second prediction may be issued that such a shock is no longer likely, allowing the magnetic disk device to switch to a normal state of operations. The shock-resistant state of the magnetic disk device can prevent data access and thus inhibit the progress of important process(es). Upon recognition that an important process is being delayed, the condition for issuing the second prediction may be relaxed to more quickly return the magnetic disk device to a normal operating state.

Abstract: The present invention registers execution modules in association with operating speed attribute data by analyzing code containing operating speed of each of the execution modules as attribute data, groups the registered execution modules by operating speed based on the associated operating speed attribute data and creates a file header containing attributes of each group, upon loading an executable file containing said file header into memory at the time of execution; associates the operating speed attribute data with an address range of the loading for each execution module in the executable file, and controls the operating speed of the processor executing an execution module according to the operating speed attribute data associated with the address of the execution module when the module is executed.

Abstract: A storage system in which a set of a data block and a redundancy block is stored has a plurality of control sections which respectively control a plurality of storages, a host connection unit which selects the control section controlling one of the storage in which a write data block which is a write-object block is to be stored, and a transfer unit which transfers the write data block to the control section. Each of the plurality of control sections includes a data block write section which writes the write data block transferred by a transfer unit to the storage in which the write data block is to be stored, a redundancy block update request section which requests the control section controlling the storage in which a redundancy block is to be stored to update the redundancy block, and a redundancy block update section which updates the redundancy block stored in the storage controlled by the control section when another of the control sections makes a request for updating the redundancy block.

Abstract: An apparatus and a method for correcting image data detected by an image sensor with less used memory space and fewer arithmetic operation executions is provided for. A data correcting apparatus of the present invention comprises an operation memory for storing expansion coefficient array data and basis function array data, which includes data of expansion coefficients and function values of a basis function for orthogonally expanding a high order polynomial for correcting input image data; and an operation part for correcting the input image data using the expansion coefficient array data and the basis function array data. With the use of the apparatus, the processing time of the operation part can also be minimized.

Abstract: A CAM system is disclosed in which requests for address translation are provided as input search data to a dynamic compare bitline generator. The dynamic compare bitline generator also receives a compare mask and applies the compare mask to associated input search data bits on a per bit basis. The mask contains information that specifies a selected page size and a selected logic mode that can be applied to a compare array in which the specified search is conducted. The compare array is coupled to a data array to which the compare array indicates a result of the search.

Abstract: A bit-read apparatus includes a first decoder and N multiplexers, each having Q output nodes and Q pull-ups coupled thereto. Respective multiplexers have M selectors coupled to N×M respective select lines and register-file cells. The selectors are in Q groups coupled to respective output nodes. Each multiplexer has a logic gate with inputs coupled to respective multiplexer output nodes. A second decoder is coupled to an N+1th multiplexer having R output nodes and R pull-ups coupled thereto. The N+1th multiplexer also has N selectors, coupled to respective select lines of the second decoder and respective output logic gates of the N multiplexers. The N selectors are in R groups coupled to the R nodes. An output logic gate for N+1th multiplexer has R inputs coupled respectively to the R nodes. Each pull-up of the multiplexers drives its respective multiplexer output node responsive to an address-bit signal.

Abstract: For testing a device under test (“DUT”) a test specification is converted in a computer system by a pin vector generator process, which includes generating test vectors. The DUT has numerous input pins and such a pin vector is for a signal to drive one such pin. The pin vectors are compressed and saved. Ones of the pin vectors are loaded, upon initialization of a test, into a pipeline having a series of memory stages and extending from the computer system to channel cards in a test head. The pipeline is operated in data transfer cycles, delivering W bits per cycle. The pin vectors are decompressed at the respective channel cards in decompressor read cycles. X bits are read per decompressor cycle, W being greater than X, so that the pipeline may perform its data transfer cycles less frequently than the decompressor performs its read cycles.

Abstract: A system, method and apparatus is provided that splits a microprocessor load instruction into two (2) parts, a speculative load instruction and a check speculative load instruction. The speculative load instruction can be moved ahead in the instruction stream by the compiler as soon as the address and result registers are available. This is true even when the data to be loaded is not actually required. This speculative load instruction will not cause a fault in the memory if the access is invalid, i.e. the load misses and a token bit is set. The check speculative load instruction will cause the speculative load instruction to be retried in the event the token bit was set equal to one. In this manner, the latency associated with branching to an interrupt routine will be eliminated a significant amount of the time. It is very possible that the reasons for invalidating the speculative load operation are no longer present (e.g. page in memory is not present) and the load will be allowed to complete.

Abstract: A memory array includes a storage unit with a number of sections and decoders coupled to respective ones of the sections for decoding an N-bit address signal and responsively asserting a signal on one of the word lines selected by the address signal. Local clock buffers are coupled to respective ones of the decoders for receiving a clock signal and an address signal including M most-significant bits of the N-bit address signal and generating respective timing signals. The decoders receive the timing signal from their respective local clock buffers. Each decoder is operable to alternately precharge and evaluate the N-bit address signal responsive to phases of the timing signal. Each local clock buffer is operable, responsive to a state of the M bits of the address signal, for selecting between holding its timing signal in a deasserted state and enabling its timing signal to follow the clock signal.

Abstract: A register-file bit read apparatus includes a decoder operable to receive a number of address-bit signals and responsively assert a select signal on one of M select lines. Each select line corresponds to a respective one of M register-file cells. The apparatus also includes a multiplexer having Q output nodes and M selectors. Each selector is coupled to one of the select lines and that select line's corresponding register-file cell. The selectors are in Q groups, each coupled to a respective one of the multiplexer's output nodes. The apparatus also includes an output logic gate having Q inputs, coupled to respective ones of the multiplexer output nodes. The multiplexer includes Q pull-ups, each of which is coupled to a respective one of the multiplexer output nodes and is operable to drive its multiplexer output node responsive to one of the address-bit signals.

Abstract: A method for receiving data by an integrated circuitry chip includes receiving data signals and a first clock signal sent by a sending chip. The data signals are received by data receivers and the clock signal is received by at least one clock receiver of the receiving chip. A reference voltage is derived by reference voltage circuitry for the receiving chip responsive to the first clock signal. Logical states of the received data signals are detected. The detecting includes the data receivers comparing voltage levels of the received data signals to the derived reference voltage.

Abstract: A method, system, and apparatus for isolating fatal data fetch errors to a single partition within a logically partitioned data processing system. In one embodiment, the logically partitioned data processing system includes a plurality of operating systems and a plurality of processors is provided. Each of the operating systems is assigned to a separate one of a plurality of logical partitions. Each of the processors is assigned to one of the plurality of logical partitions. The logically partitioned data processing system also includes a hypervisor for creating and maintaining separation of the plurality of logical partitions. The hypervisor contains services and functions accessed by each of the logical partitions and, to prevent fatal data fetch errors in one partition from effecting other partitions within the logically partitioned data processing system, the hypervisor includes a plurality of data structure areas.

Abstract: In one embodiment, a device for capturing information from a document to be input to an information handling system (“IHS”) includes a housing that a user may selectively place to reveal a first portion of the document. That is, the housing defines a viewing area, such as by defining an opening through which the first portion of the document may be viewed. The housing has a shutter for selecting a subportion of the first revealed portion of the document by shutting off a portion of the viewing area, thereby hiding a portion of the first revealed portion of the document and revealing only the selected subportion. A scanner for capturing an image of the revealed subportion of the document is movably attached to the housing. In another aspect, the input device includes a magnifying lens for displaying an enlarged view of the portion of the document revealed in the viewing area, so that a user of the input device may more precisely select the subportion of the document.

Abstract: A method for managing system firmware in a data processing system having a plurality of logical partitions is provided. Responsive to a request to update the system firmware from a first logical partition within the plurality of logical partitions in the data processing system, a determination is made whether the first logical partition within the plurality of logical partitions is present in the data processing system. Responsive to the determination that the first logical partition within the plurality of logical partitions is present in the data processing system, the system firmware is updated from the first logical partition in the data processing system. Then starting of additional partitions within the plurality of logical partitions in the data processing system is inhibited until the firmware update from the first logical partition is complete.

Abstract: A method, system and apparatus for multicasting or broadcasting a piece of data from one partition of a partitioned computer system to a plurality of partitions of the system are provided. When a partition needs to transfer data to more than one partition of the system, the partition first stores the data into a global memory accessible by all partitions of the system. The memory is then marked “read-only” to ensure that the data is not over-written and the Ids (identifications) of the recipient partitions are passed to a piece of firmware or hardware of the computer system. This firmware or hardware then alerts the recipient partitions that there is a piece of data ready to be read in the memory. Once all the recipient partitions have read the data, the global memory is reverted to a “read” and “write” memory.

Abstract: A method for prioritizing bus errors for a computing system is provided. A subsystem test is executed on a first subsystem from a plurality of subsystems on a bus system, wherein the subsystem test on the bus system is specific to the first bus subsystem. An output is received in response to executing the subsystem test. In response to the output indicating an error on the first subsystem, a severity level is assessed based on the error. For all subsystems from the plurality of subsystems on the bus system, a subsystem test is executed on each remaining subsystem, wherein each subsystem test on the bus system is specific to each remaining subsystem. An output is received in response to executing each subsystem test. In response to the output indicating an error on any of the remaining subsystems, a severity level is assessed based on the error.