Abstract: A digital interface circuit has two inverters with different switching points, one below and one above the nominal transition point of the circuit. Each inverter controls both pull-up and pull-down output transistors. The inverter with the low switching point controls the low-to-high signal transition, while the inverter with the high switching point controls the high-to-low signal transition. Pass gates responsive through delay elements to either the circuit input, an inverter output, or the circuit output isolate the other inverter from the output transistors. The pass gates may also be tristatable by means of a logical combination of the delayed pass gate enable signals with output enable signals. In yet another embodiment, the pair of inverters are replaced by a single inverter with dual switching points.

Abstract: A digital sound-producing device having a digital signal processor (DSP) and data cache memory, and using an external sample memory for storing digital audio sample data, includes a virtual cache memory block for dynamically allocating cache lines of the data cache memory. The virtual cache memory block is located in the address path between the DSP and both the data cache memory and sample memory, while the data cache memory is on the data path between the DSP and sample memory. Requests by the DSP for access to the sample memory are in the form of a virtual address corresponding to a particular sample memory address. The virtual cache memory block determines whether the virtual address already has an allocated cache line for the data cache memory, and if so transfers the requested data between that cache line and the DSP. If not, it allocates a data cache line as corresponding to the virtual address, and transfers data from the corresponding sample memory address to the cache line.

Abstract: An integrated motion control device having a controller mated to a motor body with a set of rigid, electrically conductive signal pins. The motor is direct-current and preferably brushless, and has Hall sensors within the motor body and an encoder at a back end for precisely determining rotor position. Signals from the Hall sensors and encoder are fed to a microprocessor contained in the controller and including a PID filter for servo control of the motor. The controller contains an amplifier for driving the motor and a power supply for providing appropriate levels of DC power to various elements of the controller and motor. All electrical signals between the motor and controller are transmitted via the pins, eliminating wiring harnesses of the prior art and related signal noise and wiring problems. The motor body and controller are affixed with a few screws, allowing the controller to be removed from the motor while the motor remains connected to an application.

Abstract: A field programmable gate array has a matrix of programmable logic cells and a bus network of local and express bus lines. The bus network effectively partitions the matrix into blocks of cells with each block having its own distinct set of local bus lines. Express bus lines extend across more than one block of cells by means of repeater switch units that also connect local bus lines to express bus lines. The grouping of cells into blocks with repeaters aligned in rows and columns at the borders between blocks creates spaces at the corners of blocks that can be filled with RAM blocks, other memory structures, specialized logic structures or other dedicated function elements that are connected to the bus network. The RAM blocks can be single or dual port SRAM addressed through the bus lines. Pairs of adjacent columns of RAM blocks may be commonly addressed by the same set of bus lines. Other specialized or dedicated logic might also fill those corner spaces.

Abstract: An angle-dependent reflectometer or transmissometer includes an optical imaging array in the incident and reflected or transmitted light path that breaks up an incident light beam into mutually spatially incoherent light bundles. The individual light bundles are then focused to a common spot by a high numerical aperture objective lens so as to provide a range of incidence angles on a sample surface. In a reflectometer, reflected light returns through the objective lens and imaging array and is imaged onto a detector array where different incidence and reflection angles are received by different groups of detection elements. In the angle-dependent transmissometer, the imaging array and high numerical aperture focusing objective lens are used for illuminating a spot on the sample, with a second high numerical aperture collection objective lens and detector array used for receiving transmitted light over a wide range of collection angles.

Abstract: A first output buffer circuit with independent transparent latch and tristate output capabilities includes input translators that directly drive a pair of main pull-up and pull-down output transistors. The input translators are tristatable in response to latch control signals and latching elements on side branches of the signal paths leading from the translator outputs to the output transistor gates hold the last voltage value on those signal paths at the time the translators are disabled. The main current paths through the output transistors include isolation transistors in series with the output transistors and responsive to feedback control from the buffer output. These feedback paths include logic gates responsive to output enable control signals that can shut off isolation transistors and hence put the buffer output in a high impedance state.

Abstract: Bulk operation logic circuitry for use in carrying out bulk program, erase, verify and margining operations on nonvolatile memory cells of a PLD, FPGA, flash-based microcontroller, EEPROM, flash memory device or other integrated circuit containing such cells includes a flag register for designating one or more selected blocks of cells to which the bulk operation will be limited. The bulk operation circuitry includes a controller, with a state machine and associated control logic, that distributes system clock signals and provides control signals to an instruction register, the flag register, an address register and one or more data registers to control loading of instructions and data into those registers through a serial input. The state machine is responsive to a mode signal for switching it from a normal user state into a bulk operation state.

Abstract: A nonvolatile memory device includes two floating-gate-type memory arrays, e.g. a flash memory intended to be used as a relatively permanent program memory and an E.sup.2 PROM intended to be used as a more frequently updated data memory. A single set of address lines and a single set of data lines are used for both read and write operations for both memory arrays. Address decoding means for accessing an addressed location of a selected memory array includes separate column decoders and data latches for each array, but also includes a shared row decoder common to both arrays. Row address latching circuitry associated with at least the data memory holds a decoded row address for that memory array during a write operation so as to free the shared row decoder for use on one or more concurrent read operations for the other memory array, e.g. the program memory. Data I/O buffer circuitry and sense amplifiers are also shared by both arrays.

Abstract: A dynamic termination circuit is disclosed that has a plurality of parallel termination elements that respond successively to a signal transition and which are selectively enabled and disabled to provide a desired impedance match with a transmission line. Each termination element includes a first dynamic resistive path between a voltage supply line and that termination element's output and a second dynamic resistive path between the termination element output and ground, both resistive paths including field-effect transistors whose control gates are responsive to a signal received from the transmission line via an input to the circuit. For successive response, a series of delay elements are provided between the circuit input and the respective termination circuit elements. For selective enablement, logic gates connected between the termination element inputs and the field-effect transistor control gates have enable inputs receiving user-programmable enable signals for the respective termination elements.

Abstract: An ultraviolet (UV) catadioptric imaging system, with broad spectrum correction of primary and residual, longitudinal and lateral, chromatic aberrations for wavelengths extending into the deep UV (as short as about 0.16 .mu.m), comprises a focusing lens group with multiple lens elements that provide high levels of correction of both image aberrations and chromatic variation of aberrations over a selected wavelength band, a field lens group formed from lens elements with at least two different refractive materials, such as silica and a fluoride glass, and a catadioptric group including a concave reflective surface providing most of the focusing power of the system and a thick lens providing primary color correction in combination with the focusing lens group. The field lens group is located near the intermediate image provided by the focusing lens group and functions to correct the residual chromatic aberrations. The system is characterized by a high numerical aperture (typ. greater than 0.

Abstract: A non-volatile programmable circuit having programming and read bitlines, a non-volatile memory cell, and a read select transistor, and a method for its operation. The non-volatile memory cell is programmable through the programming bitline. The read select transistor is connected between the non-volatile memory cell and the read bitline. During read operation, the programming bitline is grounded and programmed information is readable onto the read bitline. During programming operation, the read bitline is grounded, and programmed information is programmable into the non-volatile memory cell for storage and retention.

Abstract: A logic output control circuit for selecting between stored and nonstored outputs from a data input and a clock having a data pass gate MOS transistor receiving a logic signal at its data input and either blocking the signal or passing it to a cross-coupled inverter gate latch depending on a control signal at its control gate terminal. The control signal is derived in one embodiment by a logic gate with a programming signal input, a clock input and a control signal output, and in a second embodiment by a set of pass gate transistors respectively receiving a clock signal and a fixed level signal and controlled by a programming signal. When the programming signal has one logic level, the data pass transistor is always on and the logic signal flows continually to the output. When the programming signal has the other logic level, the data pass transistor switches on and off with the clock signal and the circuit operates as a latch.

Abstract: An apparatus and method using laser induced shock waves to dislodge particles from a wafer surface. The apparatus includes a wafer support, a particle detector and computer for locating and storing the locations of particles on the wafer, a laser, and focusing optics. Laser beam pulses are directed toward the wafer surface at a shallow angle or with a large beam convergence angle to avoid damage to the wafer.

Abstract: A diode laser external lens cavity configuration having a stripe mirror with two thin parallel stripes placed in front of the two lobes of the arrays for far field output pattern. The configuration includes a diode laser array or broad area laser, a lens system, such as a graded-index lens, disposed in front of the laser's front light emitting facet and the stripe mirror disposed in front of the lens system at the focal plane of the lens. The two stripes are parallel to one another on opposite sides of and equidistant from a vertical reference plane through the lens' center axis. One stripe is highly reflective, while the other is effectively only partially reflective having either a lower stripe reflectivity or shorter length than the first stripe. Other embodiments include a third stripe spaced from and collinear with the second stripe to form an etalon, and a grating in the cavity.

Abstract: GaAs/AlGaAs heterostructure lasers containing indium in at least one layer other than or in addition to the active region. Embodiments are described in which indium added in low concentration to the cladding functions to match the lattice constants between the cladding and active layers, in which indium is added in high concentration to form strain layers that prevent defect migration therethrough and if proximate to the active region decrease transparency current and increase differential gain, in which indium is added uniformly to all layers to suppress defect formation, and in which indium is added to a cap layer to reduce metallization contact resistance.