Abstract: Flush apparatus for a dual multi-processing system. Each dual multi-processing system has a number of processors, with each processor having a store in first-level write through cache to a second-level cache. A third-level memory is shared by the dual system with the first-level and second-level caches being globally addressable to all of the third-level memory. Processors can write through to the local second-level cache and have access to the remote second-level cache via the local storage controller. A coherency scheme for the dual system provides each second-level cache with indicators for each cache line showing which ones are valid and which ones have been modified or are different than what is reflected in the corresponding third level memory.

Abstract: A method and apparatus for reducing processor response time to selected transfer instructions in an multi-instruction processor. The response time is shortened by using a fast path to generate addresses for selected transfer instructions. In this fast path a base address, retained in a register from a previous instruction, is summed with an offset from the current instruction to obtain an absolute address for memory accessing. Before the fast path is entered determinations are made whether the instruction is a particular transfer instruction of a particular class and subclass, and whether the base address is different than the base address for the previous instruction. Even through the fast path is entered the usual absolute address generator path is also entered where the instruction is subjected to both high and low limit tests.

Abstract: A method and apparatus for reducing processor response time to selected transfer instructions in an instruction processor using a plurality of memory banks including four banks in a basic mode and one memory bank in an extended mode. This invention provides fast transfer hardware to improve the response time by a speed up transfer for normal extended mode transfer instructions only. The bank descriptor of the instruction is used to determine appropriate transfer instructions which are then tested for characteristics indicating whether a fast transfer is possible. The fast transfer process requires fewer checks than the previous apparatus which accelerates the response to selected transfer instructions by one cycle.

Abstract: Method and apparatus for providing backup memory storage for audit trail data within a computer system having a main memory storage, a non-volatile memory storage, and backup memory storage. The computer system executes a number of transaction programs which generate audit trail entries. As the audit trail entries are generated, a portion of the audit trail entries are stored in a portion of the main memory storage to create an audit trail. The audit trail entries are accumulated in the portion of the main memory storage until a request is received to write the portion of the main memory storage to a corresponding portion of the non-volatile memory. Subsequent portions of the audit trail entries are accumulated in subsequent portions of the main memory storage.

Abstract: Method and apparatus for managing the allocation and release of memory space within a number of files shared by a number of hosts in a data processing system. A number of allocate and release tables are provided which are accessible by the number of hosts for managing the allocation and release of space within the number of files. Each one of the number of allocate and release tables corresponds to one of the number of files and provides a file location, file size, and indication to the number of hosts of which of the number of blocks within the file have been allocated and which of the number of blocks have been released. Any host may allocate one or more of the number of blocks to store messages created or received by the host by determining from the allocate and release tables which one or more of the number of blocks within one of the number of files are available.

Abstract: A method and apparatus for incrementally optimizing a circuit design. The present invention provides an iterative EDA process that only requires the optimization, placement and routing of the actual changes made during a each design iteration, and leaves the remainder of the circuit design in a fixed state.

Abstract: An apparatus for and method of providing rapid communication between separately clocked system elements. A network interface module is used as the overall system control and communication interface to each of the separate system elements. Each of these system elements is controlled by a different and dedicated programmable micro-engine. A separate register located within and addressable by each of the micro-engines provides the basic data transfer path. Access by a micro-engine to the corresponding register is easily accomplished by firmware. The bit serial scan interface between the network interface module and each of the registers is controlled by the network interface module.

Abstract: A method and apparatus for setting a priority sequence among a plurality of requesters using a common destination within a computer system. An advantage is that all requesters contending for the common destination will have timely access with respect to all other competing requesters. In a first exemplary embodiment of the present invention, a priority controller can use a two-level priority scheme to select the next requester. The first level of priority alternates between an external requester and an on-card requester where every other set of data is from the external requester. The second level of priority alternates between on-card modules during an on-card priority cycle. In an alternative exemplary embodiment, the priority controller can stack a request to transfer acknowledge and data information from an external requester if it is busy. The priority controller also prevents sending an acknowledgment/data cycle out to an external source to prevent sending more data than the FIFO stacks can accommodate.

Abstract: A method and apparatus for providing optimization parameters to an EDA logic optimizing tool. The optimization parameters for selected circuit modules within a circuit design database may be stored such that a particular optimization parameter set can be uniquely identified by a search capability of a data processing system, thereby enabling the logic optimizer tool to select and access a particular optimization parameter set from a collection of optimization parameter sets. Further, the optimization parameters may be stored such that the corresponding optimization parameters can be collectively viewed by a circuit designer.

Abstract: Method and apparatus for a computer system to efficiently operate with multiple instruction processors and input/output subsystem in a symmetrical multi-processing environment. The computer system uses a new storage controller having a high performance interconnect scheme that scales in system performance as additional common storage controller modules are added. The interconnect scheme has the cost advantage of a bus connected system while achieving the performance characteristics of a crossbar connected system.

Abstract: A data processing system including a first and second host, a first and second outboard file cache connected to the first host, and a first and second secondary storage device connected to the first host. The system operation includes the first host reading file data from the first or second secondary storage device after the data is cached on both the first and second outboard file caches. File data is updated by writing to both first and second outboard file caches. File data is destaged by writing data from the first outboard file cache only, to first and second secondary storage devices. Failure of a single outboard file cache is handled by the first host not reading and writing to the failed outboard file cache. Site-wide failure of first host, first outboard file cache, and first secondary storage device is handled by establishing communication from second host to both second outboard file cache and second secondary storage device and resuming processing.

Abstract: Method and apparatus for maximizing cache memory throughput in a system where a plurality of requesters may contend for access to a same memory simultaneously. The memory utilizes an interleaved addressing scheme wherein each memory segment is associated with a separate queuing structure and the memory is mapped noncontiguously within the same segment so that all segments are accessed equally. Throughput is maximized as the plurality of requesters are queued evenly throughout the system.

Abstract: A method and apparatus for monitoring the performance of a circuit optimization tool. The present invention contemplates inserting a number of performance monitoring commands into selected ones of a number of optimization scripts, wherein selected ones of the performance monitoring commands provide a number of performance related results when executed. Thereafter, the number of optimization scripts may be executed to optimize the circuit design. The number of results provided by the performance monitoring commands may then be assembled and analyzed by the circuit designer to identify any performance related problems.

Abstract: A system and methodology for implementing user assistance functions concerning interoperability of diverse applications, whether hosted on the same computer platform or hosted on different computer platforms. The user is assisted by being offered information, tools and/or automation as appropriate to the problem presented. As appropriate, graphics or animation is utilized to permit complete and full understanding by the user of the assistance being provided.