Abstract: The present invention relates to improvements in the operation and construction of roof bolters or roof bolt installation apparatus. The improvements comprise a roof bolter constructed so that the critical moving parts of its timber jack, feed frame, feed carrier and rotational unit are comprised of a rod and sleeve construction. Such construction allowing the protection of surfaces. The construction also includes feature of a spaced apart rod and sleeve construction which allows motive power units to be housed within the confines of the timber jack and feed carrier. The spaced apart arrangement also provides stability to the roof bolter.

Abstract: A memory and sense amplifier with latched output included therein derives high speed and noise immunity with precharged logic circuits through the separation of sense amplifier enablement and resetting by use of the precharge operation. Inclusion of bit line decoders which are wholly or partially self-resetting and self-precharging in sense amplifier support circuitry allows high performance at extremely short memory operation cycle times. A multiplexor is included which is usable in operating cycles as well as test cycles of the memory and further, in combination with other elements of the memory and sense amplifier arrangement, enables the pipelining of plural memory operations in a single memory cycle.

Abstract: Disclosed is a combined antenna and helicopter rotor blade. The antenna has one or more electrically non-conductive rotor blades, each having an electrical conductor positioned parallel to the major axis of a respective rotor blade. An electrical connection is provided to connect the antenna to a radio for the reception or transmission of radio waves. Also disclosed is a communications system including apparatus for the transmission or reception of radio waves. Two of the electrical conductors, having angular positions nearer to a predetermined angular position are connected via the electrical connector to the radio. The remaining conductors may either be connected to the body of the helicopter or supplied with a signal out of phase compared to that supplied to the two electrical conductors.

Abstract: A processor functioning as a coprocessor attached to a central processing complex provides efficient execution of the functions required for database processing: sorting, merging, joining, searching and manipulating fields in a host memory system. The specialized functional units: a memory interface and field extractor/assembler, a Predicate Evaluator, a combined sort/merge/join unit, a hasher, and a microcoded control processor, are all centered around a partitioned Working Store. Each functional unit is pipelined and optimized according to the function it performs, and executes its portion of the query efficiently. All functional units execute simultaneously under the control processor to achieve the desired results. Many different database functions can be performed by chaining simple operations together. The processor can effectively replace the CPU bound portions of complex database operations with functions that run at the maximum memory access rate improving performance on complex queries.

Abstract: A processor functioning as a coprocessor attached to a central processing complex provides efficient execution of the functions required for database processing: sorting, merging, joining, searching and manipulating fields in a host memory system. The specialized functional units: a memory interface and field extractor/assembler, a Predicate Evaluator, a combined sort/merge/join unit, a hasher, and a microcoded control processor, are all centered around a partitioned Working Store. Each functional unit is pipelined and optimized according to the function it performs, and executes its portion of the query efficiently. All functional units execute simultaneously under the control processor to achieve the desired results. Many different database functions can be performed by chaining simple operations together. The processor can effectively replace the CPU bound portions of complex database operations with functions that run at the maximum memory access rate improving performance on complex queries.

Abstract: A processor functioning as a coprocessor attached to a central processing complex provides efficient execution of the functions required for database processing: sorting, merging, joining, searching and manipulating fields in a host memory system. The specialized functional units: a memory interface and field extractor/assembler, a Predicate Evaluator, a combined sort/merge/join unit, a hasher, and a microcoded control processor, are all centered around a partitioned Working Store. Each functional unit is pipelined and optimized according to the function it performs, and executes its portion of the query efficiently. All functional units execute simultaneously under the control processor to achieve the desired results. Many different database functions can be performed by chaining simple operations together. The processor can effectively replace the CPU bound portions of complex database operations with functions that run at the maximum memory access rate improving performance on complex queries.

Abstract: A processor functioning as a coprocessor attached to a central processing complex provides efficient execution of the functions required for database processing: sorting, merging, joining, searching and manipulating fields in a host memory system. The specialized. functional units: a memory interface and field extractor/assembler, a Predicate Evaluator, a combined sort/merge/join unit, a hasher, and a microcoded control processor, are all centered around a partitioned Working Store. Each functional unit is pipelined and optimized according to the function it performs, and executes its portion of the query efficiently. All functional units execute simultaneously under the control processor to achieve the desired results. Many different database functions can be performed by chaining simple operations together. The processor can effectively replace the CPU bound portions of complex database operations with functions that run at the maximum memory access rate improving performance on complex queries.

Abstract: A processor functioning as a coprocessor attached to a central processing complex provides efficient execution of the functions required for database processing: sorting, merging, joining, searching and manipulating fields in a host memory system. The specialized functional units: a memory interface and field extractor/assembler, a Predicate Evaluator, a combined sort/merge/join unit, a hasher, and a microcoded control processor, are all centered around a partitioned Working Store. Each functional unit is pipelined and optimized according to the function it performs, and executes its portion of the query efficiently. All functional units execute simultaneously under the control processor to achieve the desired results. Many different database functions can be performed by chaining simple operations together. The processor can effectively replace the CPU bound portions of complex database operations with functions that run at the maximum memory access rate improving performance on complex queries.

Abstract: A processor functioning as a coprocessor attached to a central processing complex provides efficient execution of the functions required for database processing: sorting, merging, joining, searching and manipulating fields in a host memory system. The specialized functional units: a memory interface and field extractor/assembler, a Predicate Evaluator, a combined sort/merge/join unit, a hasher, and a microcoded control processor, are all centered around a partitioned Working Store. Each functional unit is pipelined and optimized according to the function it performs, and executes its portion of the query efficiently. All functional units execute simultaneously under the control processor to achieve the desired results. Many different database functions can be performed by chaining simple operations together. The processor can effectively replace the CPU bound portions of complex database operations with functions that run at the maximum memory access rate improving performance on complex queries.

Abstract: A memory and sense amplifier with latched output included therein derives high speed and noise immunity with precharged logic circuits through the separation of sense amplifier enablement and resetting by use of the precharge operation. Inclusion of bit line decoders which are wholly or partially self-resetting and self-precharging in sense amplifier support circuitry allows high performance at extremely short memory operation cycle times. A multiplexor is included which is usable in operating cycles as well as test cycles of the memory and further, in combination with other elements of the memory and sense amplifier arrangement, enables the pipelining of plural memory operations in a single memory cycle.

Abstract: Addition of gated buffers which are accessible by the test apparatus microprocessor for receiving status information and the signals on some of the lines of the data bus of a microprocessor-based system under test provides the capacity for self testing, automatic calibration, improved diagnostics of a kernel at low levels of kernel operability and faster operation of the test system.

Abstract: A method and apparatus for providing automatic verification of the kernel circuitry of a microprocessor-based system in which the microprocessor (.mu.P) include an instruction prefetch feature. During testing by memory emulation, the memory addresses accessed by the .mu.P are evaluated as to type of access, address and data size in accordance with a test program and a corresponding checking table to determine if such accesses are consistent with a funtional .mu.P of the same type. Other data structures such as flags and pointers are provided to enhance the verification operation and use of the checking table.

Abstract: An apparatus, method and data structure for validating the data bus of a microprocessor-based unit under test in which bit patterns having half as many bits as the width of the data bus are applied to the data bus along with another bit pattern which is either the complemented or true replication of the bit pattern. Evaluation of the resulting bit patterns on the data bus permits a validation of the entire width of the data bus which, if no faults are reported, obviates not only probing of the data bus by the operator but data bus diagnosis, as well. A particular data structure of a preferred bit pattern sequence avoids any fault on any data line being reported as a pass.

Abstract: A coherent direct digital waveform synthesizer, capable of generating a waveform in response to a decimally or other non-binary related reference frequency while obtaining the advantages of the use of a binary radix phase accumulator generating binary addresses for a waveform memory. The interface between these elements include a frequency converter including a voltage controlled oscillator and a further binary radix phase accumulator in the feedback path of a phase locked loop. A binary radix related digital waveform synthesizer may be thus made to produce non-binary related frequency waveforms coherent with a non-binary radix reference frequency source, and of decimal or other non-binary radix related resolution.