Abstract: A method for reporting timing exception status is presented. The method begins by computing a set of edges of a sub-domain and a set of edges of a timing exception. A slack value is computed based on either the edges of the sub-domain common to the set of edges of the timing exception or the timing paths of the sub-domain. If the sub-domain has a valid slack value, the method compares the sub-domain timing exception type to the timing exception type of the timing exception. The method identifies the timing exception as being overridden if both timing exception types are different and either the slack value computed based on edges of the sub-domain is valid, or the sub-domain has the valid slack value and an intersection of the set of edges of the sub-domain and of the timing exception forms a timing path. The method presents the overridden timing exceptions.

Abstract: Apparatuses for reducing power consumption in a programmable logic device (PLD) with a self power down mechanism are disclosed. Methods and a machine readable medium for restoring a prior known state are provided. The prior known state is stored in a memory module before the PLD is powered down and the same state is restored from the memory module when the PLD is powered up. The memory module may be an internal or an external non-volatile or volatile memory source. One sector of the memory may be used to store the previous known state. The memory sector can be partitioned into different sections. One section may be used as a header section associated with a data storage section. Partitioning the memory sector into different sections and utilizing multiple addresses from each section ensure less read and write cycles during the powering down and the powering up of the PLD.

Abstract: First and second electrodes are disposed at first and second locations, respectively, proximate to a periphery of a wafer support, wherein the first and second location are substantially opposed to each other relative to the wafer support. Each of the first and second electrodes can be moved to electrically connect with and disconnect from a wafer held by the wafer support. An anode is disposed over and proximate to the wafer such that a meniscus of electroplating solution is maintained between the anode and the wafer. As the anode moves over the wafer from the first location to the second location, an electric current is applied through the meniscus between the anode and the wafer. Also, as the anode is moved over the wafer, the first and second electrodes are controlled to connect with the wafer while ensuring that the anode does not pass over an electrode that is connected.

Abstract: A computer-implemented method and computer-readable medium for providing object-oriented communication between isolates is described. A request is received from a requesting Xlet for a remote reference to an exported object in a first isolate, the exported object having been exported by an exporting Xlet. A plurality of object registries are searched for the remote reference, each of the object registries being in a respective isolate. The remote reference is retrieved from one of the object registries and the remote reference is forwarded to the requesting Xlet.

Abstract: Disclosed are a system and method with a cooperative control algorithm that can appraise voltage stability of a power system in cooperation with a supervisory control and data acquisition (SCADA)/emergency management system (EMS) for cooperative control on multiple parallel flexible alternating current transmission systems (FACTS) to enhance voltage stability, and that can calculate individual operation points of the FACTS.

Abstract: A method for cleaning a substrate is provided. In this method, a flow of non-Newtonian fluid is provided where at least a portion of the flow exhibits plug flow. To remove particles from a surface of the substrate, the surface of the substrate is placed in contact with the portion of the flow that exhibits plug flow such that the portion of the flow exhibiting plug flow moves over the surface of the substrate. Additional methods and apparatuses for cleaning a substrate also are described.

Abstract: A plurality of devices, such as devices that are utilized for implementing radio frequency applications, can be formed in the same substrate. Each of these devices may be formed over a triple well that includes at least one well capable of being biased. Each of the wells is coupled to a well bias through a resistor. In some embodiments, a plurality of wells operating at a relatively high frequency may be connected to the same bias potential, each through separate resistors. The noise coupling may be reduced through the use of the bias resistors.

Abstract: The image processing device performs image processing using image data generated by an image generating device, and image generation record information associated with the image data where the image generation record information includes at least operating information about the image generating device at the time of generation of the image data. A picture quality adjuster is able, when the image generation record information includes subject brightness information relating to the brightness of a subject at the time of generation of the image data, to adjust the picture quality of the image data using the subject brightness level derived from the subject brightness information.

Abstract: When a memory card is inserted into a slot, the control circuit of a color printer obtains image output control information from a memory card and analyzes it. When auto light source is not set as the light source, the CPU references the reference values and coefficients for the characteristics parameters except for color balance and performs correction, and then adjusts the image data image quality to reflect the post-correction characteristics parameters. As a result, it is possible to automatically adjust the image quality of image data without losing the selectively set output conditions.

Abstract: A flash memory system includes a flash controller for controlling operation of at least two flash memory devices. A page buffer is allocated within each flash memory device, such that one page buffer functions as a designated target buffer and another page buffer functions as a mirror buffer. The flash controller transmits the page data to two flash memory devices simultaneously, such that no backup of the page data is required to be kept in the flash controller. Hence, there is no delay in writing the next page data from a host computer to the flash controller.

Abstract: A method for optimizing signal operating parameters for a signal sent over a data transmission channel through a programmable logic device (PLD) is provided. A transmit test pattern is generated and is associated with a set of signal operating parameters for the transmission and receiving of the test pattern over a data transmission channel. The data transmission channel loops from a transmit port to a receive port of the PLD. A determination of whether the received test pattern matches the transmit test pattern is performed. The match results and the set of signal operating parameters are recorded. At least one of the signal operating parameters of the set of signal operating parameters is modified through a processor of the PLD. Another transmit pattern is transmitted and received according to the modified set of signal operating parameters and the results are recorded. Methods for optimizing data transfer into a PLD and corresponding apparatuses are included.

Abstract: A method for identifying specification window violations for a system is described. The method includes generating a sample set of input parameters. The system is simulated using the sample set to generate an output set. A mathematical model is best-fit to the output set. A set of desirability functions is defined to an out-of-spec condition. The model is then searched using the desirability functions to identify a worst-case data point. The worst-case data point can then be determined as either being within specification or out of specification.

Abstract: The present invention discloses methods for delivering code to a host system including the steps of: accepting a CPU request, from a host-system processor of the host system, for a code segment; initiating a retrieval process to retrieve the code segment; upon expiration of a predetermined time, checking whether the code segment is ready for delivery; upon the predetermined time expiring before the code segment is ready for delivery, providing an SWI that is different than the code segment; and upon the predetermined time expiring after the code segment is ready for delivery, providing the code segment. Preferably, the SWI causes the host-system processor to jump to a reset-vector address. Most preferably, the reset-vector code, located at the reset-vector address, includes a command to request the code segment again.

Abstract: A method for dependent trust in a computer system is provided. In this method, trust dependency relationships are defined among components of the computer system, specifying, for a component, which components it relies on in ensuring the integrity or confidentiality of its code or data. Subsequently, trust dependencies are resolved and the results are used in performing certain operations described in Trusted Computing Group standards including generating an attestation reply, sealing data, and unsealing data. In addition, methods for computing an integrity measurement for a Core Root of Trust for Measurement of a trust-dependent component are included. A system for dependent trust in a computer system is also described.

Abstract: In one embodiment an input device is provided. The input device includes a central body. A response and communications system is included in the input device. The response and communication system enables communication between the input device and a computing device. At least one protrusion extending from the central body are included. The central body and the at least one protrusion are configured to capture a user's hand movements. The input device is configured to be held by the user. An input detection program, a computing system, computer program instructions and a method for communicating commands to a computer system from an external input device are provided.

Abstract: An improved memory card includes an interface for receiving content from an appliance, a primary memory, a secondary memory, and primary controller. The primary controller is configured to selectively write the content only on the primary memory card, or only on the secondary memory card, or on both memories. The improved memory card also includes an enclosure for enclosing the primary memory, the secondary memory, the primary host interface and the primary controller. The improved memory card also includes a user interface that includes a user-operable mode switch that is switchable between a “full capacity” mode and a “full redundancy” mode. In the “full capacity” mode the secondary memory is used for recording genuine content, whereas in the “full redundancy” mode the secondary memory is used for backing up content that has been recorded on the primary memory. A digital shoebox is also provided, which can use improved memory cards and conventional memory cards alike for archiving content.

Abstract: A semiconductor device includes a substrate portion having a plurality of diffusion regions defined in a non-symmetrical manner relative to a virtual line defined to bisect the substrate portion. A gate electrode level region is formed above the substrate portion to include a number of conductive features defined to extend in only a first parallel direction and fabricated from a respective originating rectangular-shaped layout feature. The gate electrode level region includes conductive features defined along at least four different virtual lines of extent in the first parallel direction. A width size of the conductive features within the gate electrode level region is measured perpendicular to the first parallel direction. Within a five wavelength photolithographic interaction radius within the gate electrode level region, the width size of the conductive features is less than 193 nanometers, which is the wavelength of light used in a photolithography process to fabricate the conductive features.

Abstract: A method for high-speed scheduling and arbitration of events for computing and networking is disclosed. The method includes the software and hardware implementation of a unique data structure, known as a pile, for scheduling and arbitration of events. According to the method, events are stored in loosely sorted order in piles, with the next event to be processed residing in the root node of the pile. The pipelining of the insertion and removal of events from the piles allows for simultaneous event removal and next event calculation. The method's inherent parallelisms thus allow for the automatic rescheduling of removed events for re-execution at a future time, also known as event swapping. The method executes in O(1) time.

Abstract: A semiconductor device includes a substrate portion that includes a plurality of diffusion regions that include at least one p-type diffusion region and at least one n-type diffusion region. A gate electrode level region is formed above the substrate portion to include a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level region is fabricated from a respective originating rectangular-shaped layout feature. Each of the conductive features within the gate electrode level region has a width less than a wavelength of light used in a photolithography process to fabricate the conductive features. Conductive features within the gate electrode level region form respective PMOS transistor devices and respective NMOS transistor devices. A total number of the PMOS transistor devices and the NMOS transistor devices in the gate electrode level region is greater than or equal to eight.

Abstract: A storage system for exchanging data with a host system, the storage system including a plurality of storage devices, each of the storage devices including: a non-volatile memory, wherein a fixed static-IP address resides in the non-volatile memory, the fixed static-IP address being common to two or more of the plurality of storage devices, and the fixed static-IP address providing enablement of a storage-device functionality of the storage device; a physical interface for operationally connecting the storage device with the host system; and a memory controller for: controlling the respective non-volatile memory; and exchanging data, using a communication protocol, via the respective fixed static-IP address. For at least one of the storage devices, the respective fixed static-IP address may be pre-loaded into the respective non-volatile memory during manufacture, or installed in the respective non-volatile memory after manufacture.