Patents Represented by Attorney, Agent or Law Firm Martine Penilla & Kim, LLP
  • Patent number: 6165255
    Abstract: A chemical-liquid controlling apparatus is described. The chemical-liquid controlling apparatus is mounted between a chemical-liquid container and an exhaust apparatus. During a chemical-liquid refilling process, once the chemical liquid is drawn out of the container by the exhaust apparatus, the chemical liquid first enters the chemical-liquid controlling apparatus. The chemical-liquid controlling apparatus separates the chemical liquid from a nitrogen gas and a chemical gas. In addition, the chemical-liquid refilling process is stopped by a signal transmitted from a leak sensor.
    Type: Grant
    Filed: March 12, 1999
    Date of Patent: December 26, 2000
    Assignee: United Microelectronics Corp.
    Inventors: Chien-Hsin Lai, Peng-Yih Peng, Li-Min Chang, Fu-Yang Yu
  • Patent number: 6163289
    Abstract: A digital-to-analog converter with differential output voltage includes a resistor string with high and low reference voltages end nodes and with nodes located between adjacent resistors of the string, first switches of a first analog multiplexer for deriving first divided voltages from first nodes of the resistor string, second switches of a second analog multiplexer for deriving second divided voltages from second nodes of the resistor string, and a decoder device receiving a digital signal. The decoder device is coupled to the first switches for selecting the first switches according to a first code derived from a first bit portion of the digital signal, and the decoder device is coupled to the second switches for selecting the second switches according to a second code derived from a second bit portion of the digital signal different to the first bit portion, whereby a selected first divided voltage and a selected second divided voltage define a selected differential output voltage of the converter.
    Type: Grant
    Filed: September 23, 1998
    Date of Patent: December 19, 2000
    Assignee: Philips Electronics North America Corp.
    Inventor: Bernard Ginetti
  • Patent number: 6162301
    Abstract: A cleaning solution, method, and apparatus for cleaning semiconductor substrates after chemical mechanical polishing of copper films is described. The present invention includes a cleaning solution which combines deionized water, an organic compound, and a fluoride compound in an acidic pH environment for cleaning the surface of a semiconductor substrate after polishing a copper layer. Such methods of cleaning semiconductor substrates after copper CMP alleviate the problems associated with brush loading and surface and subsurface contamination.
    Type: Grant
    Filed: January 7, 1999
    Date of Patent: December 19, 2000
    Assignee: Lam Research Corporation
    Inventors: Liming Zhang, Yuexing Zhao, Diane J. Hymes, Wilbur C. Krusell
  • Patent number: 6162586
    Abstract: Disclosed is a method for making a metallization layered stack over an oxide layer of a semiconductor substrate, and a metallization layered stack that assists in providing superior deep UV photolithography resolution. The method includes forming a bottom titanium nitride layer over the oxide layer, and forming an aluminum metallization layer over the bottom titanium nitride layer. The method further includes forming a top titanium nitride layer over the aluminum metallization layer, such that the forming of the top titanium nitride layer includes: (a) placing the semiconductor substrate in an ionized metal plasma chamber having an RF powered coil and a titanium target; (b) introducing an argon gas and a nitrogen gas into the ionized metal plasma chamber; (c) pressuring up the ionized metal plasma chamber to a pressure of between about 10 mTorr and about 50 mTorr, whereby the top titanium nitride layer is formed as a dense titanium nitride film.
    Type: Grant
    Filed: May 6, 1998
    Date of Patent: December 19, 2000
    Assignee: Philips Electronics North America Corp.
    Inventors: Samit S. Sengupta, Daniel C. Baker, Subhas Bothra
  • Patent number: 6162731
    Abstract: A method of defining the conductive layer is described in which a substrate comprises a dielectric layer and a conductive layer is formed covering the entire substrate. A common photolithography and etching process is conducted to form a wide trench pattern. An adjustment structure is also formed next to the sidewall on both sides of the trench such that the distance between the adjustment structures is same as the desired width of the conductive structure. After which, a cover layer is formed to fill the trench. Using the cover layer as a self-aligned hard mask, an anisotropic etching process is conducted to form a conductive structure.
    Type: Grant
    Filed: June 8, 1999
    Date of Patent: December 19, 2000
    Assignees: United Silicon Incorporated, United Microelectronics Corp.
    Inventor: Kuan-Yang Liao
  • Patent number: 6163871
    Abstract: Encoders, syndrome generators, and methods for generating ECC check bytes and partial syndromes from a user data sector using a single RAM unit. The user data includes a plurality of data bytes. The encoder includes a storage unit and encoder circuitry. The storage unit is configured to receive and store a plurality of interim check bytes. The encoder circuitry is configured to receive the data bytes of the user data sector sequentially and the interim check bytes to generate a plurality of new interim check bytes in accordance with a generator polynomial. The new interim check bytes is generated after each data bytes of the data sector is received. The encoder circuitry is arranged to receive the interim check bytes from the storage unit such that the encoder circuitry generates the new interim check bytes and stores the generated new interim check bytes in the storage unit as the interim check bytes.
    Type: Grant
    Filed: May 29, 1998
    Date of Patent: December 19, 2000
    Assignee: Adaptec, Inc.
    Inventor: Honda Yang
  • Patent number: 6159844
    Abstract: Disclosed is a method for fabricating conductive contacts in a dielectric layer that overlies a semiconductor wafer having diffusion regions, shallow trench isolation regions, and gate structures that have a part overlying the shallow trench isolation regions. The method includes forming an oxide layer over the gate structures and forming a photoresist mask over the semiconductor wafer, including the oxide layer over the gate structures. The photoresist mask has windows that define an opening over gate contact locations, and the gate contact locations are defined substantially over the part of the gate structures that overlie the shallow trench isolation regions. The method further includes etching the oxide layer over the gate structures through the windows to define exposed gate structure regions.
    Type: Grant
    Filed: May 29, 1998
    Date of Patent: December 12, 2000
    Assignee: Philips Electronics North America Corp.
    Inventor: Subhas Bothra
  • Patent number: 6158002
    Abstract: A system for enabling booting to a desired drive of a computer system having a floppy drive, an IDE/EIDE storage drive, and a SCSI storage drive. The system includes a floppy disk that is configured to be inserted into the floppy drive. The floppy disk contains a media containing program instructions that are configured to be executed upon initiating a system BIOS of the computer system. The execution of the program instructions includes executing a boot code stored on the media of the floppy disk. The boot code is configured to scan a number of PCI buses of the computer system to identify host adapters that are connected to respective ones of the number of PCI buses. Further, the system includes executing a BIOS code for each of the host adapters which causes an assignment of drive numbers to devices connected to the host adapters and the computer system. Then, swapping the assignment of drive numbers such that the desired drive is assigned a drive number 80h.
    Type: Grant
    Filed: August 14, 1998
    Date of Patent: December 5, 2000
    Assignee: Adaptec, Inc.
    Inventors: Tony G. Kwan, Yafu J. Ding
  • Patent number: 6156626
    Abstract: A process and system for connecting a semiconductor chip to a substrate is provided. The process includes providing the substrate that is configured to receive the semiconductor chip that has a bonding pad. The substrate has a first side that is suited to be connected to the semiconductor chip and a second side that is opposite the first side. The process then includes designing a metallization bonding structure on the first side of the substrate. The metallization bonding structure has a first end, a second end, and a bend defined between the first end and the second end. Then, an oxide passivation layer is defined over the first side that includes the metallization bonding structure. A bonding via is then defined through the passivation layer. The bonding via is configured to be aligned with the bend of the metallization bonding structure.
    Type: Grant
    Filed: February 27, 1999
    Date of Patent: December 5, 2000
    Assignee: Philips Electronics North America Corp.
    Inventor: Subhas Bothra
  • Patent number: 6153531
    Abstract: Disclosed is a method for fabricating reliable interconnect structures on a semiconductor substrate that has at least a first dielectric layer, a first patterned metallization layer, a second dielectric layer over the first patterned metallization layer, and a plurality of tungsten plugs formed in the second dielectric layer. The method includes patterning a second metallization layer that overlies the second dielectric layer and the plurality of tungsten plugs, such that the patterning leaves at least one of the plurality of tungsten plugs not completely covered by the second metallization layer. Submersing the semiconductor substrate into a dilute nitric acid solution until a passivating tungsten oxide is formed over a portion of the at least one of the plurality of tungsten plugs that is not completely covered by the second metallization layer.
    Type: Grant
    Filed: December 22, 1997
    Date of Patent: November 28, 2000
    Assignee: Philips Electronics North America Corporation
    Inventors: Subhas Bothra, Jay Patel
  • Patent number: 6154067
    Abstract: When more than two terminators are on a SCSI bus the bus is said to be "over-terminated", and when less than two terminators are on the bus, the bus is said to be "under-terminated". When the SCSI bus is either under or over terminated, the bus does not function, and often the user does not know why the bus is not functioning. Apparatus and a method are provided for indicating to the user when the bus is not properly terminated. A terminator monitoring system and method operate in conjunction with the bus. A precision resistor is connectable to the bus so that a voltage drop is produced across the precision resistor. A circuit monitors the value of the produced voltage drop across the precision resistor to provide an indication of the number of terminators on the bus. A switch selectably connects the precision resistor to the bus, and there is a source of a reference voltage.
    Type: Grant
    Filed: August 5, 1998
    Date of Patent: November 28, 2000
    Assignee: Adaptec, Inc.
    Inventor: Peter K. Cheung
  • Patent number: 6150261
    Abstract: A method of fabricating a semiconductor device for preventing an antenna effect. In the invention, there is no additional mask layer or specific process performed. Thus, the fabrication cost does not increase. In addition, extra electrons are released through a path formed in the invention during the plasma-etching step. An antenna effect thus does not occur. The reliability of the semiconductor device is increased.
    Type: Grant
    Filed: May 25, 1999
    Date of Patent: November 21, 2000
    Assignee: United Microelectronics Corp.
    Inventors: Chen-Chung Hsu, Yih-Jau Chang
  • Patent number: 6146996
    Abstract: A semiconductor device includes a semiconductor substrate, e.g., a part of a silicon wafer having an oxide layer disposed thereon. A metal stack is disposed over the semiconductor substrate and a dielectric layer is disposed over the metal stack. The dielectric layer has a via hole formed therein that is misaligned with the metal stack such that a portion of the via hole extends beyond the top of the metal stack and exposes at least a portion of one of the sidewalls of the metal stack. A sidewall cap layer is formed on the exposed portion of the sidewall of the metal stack. The sidewall cap layer is configured to resist substantial penetration of WF.sub.6 during chemical vapor deposition of tungsten. The sidewall cap layer may be a nitrided layer or a layer of a dielectric material. A conductive material comprised of tungsten is disposed in and substantially fills the via hole. Methods for making a conductive via in a semiconductor device are also described.
    Type: Grant
    Filed: September 1, 1998
    Date of Patent: November 14, 2000
    Assignee: Philips Electronics North America Corp.
    Inventor: Samit Sengupta
  • Patent number: 6145148
    Abstract: A cleaning method and apparatus using very dilute hydrofluoric acid (BF) for cleaning silicon wafers and semiconductor substrates. The HF is delivered to the core of a brush where the solution is absorbed by the brush and then applied by the brush onto the substrate. This delivery system applies the chemical solutions uniformly to the semiconductor substrate and reduces the volumes of chemical solutions used in a scrubbing process. The process of the present invention uses very dilute HF and allows a thin oxide to be etched but not completely removed so as to maintain a hydrophilic surface state. Thus, this invention presents a chemical mechanical cleaning process with in-situ etching with the use of PVA brushes on a brush scrubber. Very accurate control of etch rate is obtained and, therefore, makes this process suitable to multiple cleaning applications of silicon wafers and semiconductor substrates.
    Type: Grant
    Filed: January 7, 1999
    Date of Patent: November 14, 2000
    Assignee: Lam Research Corporation
    Inventors: Diane J. Hymes, Michael Ravkin, Xiuhua Zhang, Wilbur C. Krusell
  • Patent number: 6143089
    Abstract: A method and apparatus for cleaning a wafer oriented vertically is provided. The apparatus includes a first brush and a second brush located horizontally from the first brush. During use, a wafer is orientated vertically between the first and second brushes. The brushes are brought into contact with the wafer and rotated thereby engaging the wafer with rollers. By rotating the rollers, the wafer is also rotated. Liquid is sprayed towards the brushes and wafer. By orienting the wafer vertically, liquid and particulates contained therein readily fall from the wafer due to gravity. This is particularly advantageous when cleaning larger diameter wafers in which particulates must be removed from a larger wafer surface area.
    Type: Grant
    Filed: July 29, 1998
    Date of Patent: November 7, 2000
    Assignee: Lam Research Corporation
    Inventors: Donald Edgar Stephens, Oliver David Jones, Hugo John Miller, III
  • Patent number: 6143642
    Abstract: Disclosed is a method for making a programmable structure on a semiconductor substrate. The semiconductor structure has a first dielectric layer. The method includes plasma patterning a first metallization layer over the first dielectric layer. Forming a second dielectric layer over the first metallization layer and the first dielectric layer. Forming a plurality of tungsten plugs in the second dielectric layer. Each of the plurality of tungsten plugs are in electrical contact with the first metallization layer. Plasma patterning a second metallization layer over the second dielectric layer and the plurality of tungsten plugs, such that at least a gap over each of the tungsten plugs is not covered by the second metallization layer. Applying a programming electron dose to a portion of the second metallization layer.
    Type: Grant
    Filed: December 22, 1997
    Date of Patent: November 7, 2000
    Assignee: VLSI Technology, Inc.
    Inventors: Harlan Lee Sur, Jr., Subhas Bothra
  • Patent number: 6144223
    Abstract: A high-speed SCSI input receiver has separate high and low level input buffers, each operating in response to a control voltage that conditions their respective high and low level switching threshold voltages to remain stable about their design values without regard to temperature and process parameter variations. Each of the input buffers includes an input invertor with n-channel and p-channel current source transistors coupled between the output and the respective supply rails. A master circuit includes circuitry that substantially matches the operative circuitry of the input buffer, except that the input and output of the master circuit's invertor element are coupled together so as to define the elements actual switching threshold voltage. This threshold voltage is compared to a design threshold voltage defined by a resistor divider in a comparator.
    Type: Grant
    Filed: March 15, 2000
    Date of Patent: November 7, 2000
    Assignee: Adaptec, Inc.
    Inventor: Afshin D. Momtaz
  • Patent number: 6139702
    Abstract: A seasoning process for an etcher which is performed before etching a dielectric layer to expose a metal silicide layer. The seasoning process includes the first plasma sputtering process and the second plasma sputtering process. A wafer containing the metal silicide layer thereon is placed in the etcher with an etchant and the first plasma sputtering process is performed. Several silicon wafers are successively placed in the etcher to perform the second plasma sputtering process.
    Type: Grant
    Filed: March 5, 1999
    Date of Patent: October 31, 2000
    Assignee: United Microelectronics Corp.
    Inventors: Chan-Lon Yang, Tong-Yu Chen, Michael W C Huang
  • Patent number: 6140156
    Abstract: A method for fabricating a photodiode is described in which a pad oxide layer and a silicon nitride layer are sequentially formed on a provided substrate. The silicon nitride layer, and the pad oxide layer and the substrate are sequentially patterned to form an opening in the substrate. A spacer is formed on the sidewall of the opening. With the spacer and the silicon nitride layer serving as a mask, the substrate is etched forming a trench in the substrate. An oxide plug is then formed filling the trench and the opening using the conventional shallow trench fabrication method. A P-well region and an N-well region are formed respectively on two sides of the trench.
    Type: Grant
    Filed: July 13, 1999
    Date of Patent: October 31, 2000
    Assignee: United Microelectronics Corp.
    Inventor: Meng-Jin Tsai
  • Patent number: 6133635
    Abstract: Disclosed is a process for making a self-aligning conductive via structure in a semiconductor device. The process includes forming a first interconnect metallization layer over an oxide layer. Forming an etch stop layer over the first interconnect metallization layer. Forming a conductive via metallization layer over the etch stop layer. Forming a hard mask layer over the conductive via metallization layer. The process further includes producing a conductive via and an interconnect line, where the conductive via is formed from a portion of the conductive via metallization layer, and the interconnect line is formed from a portion of the first interconnect metallization layer. The conductive via is substantially aligned with the underlying interconnect line.
    Type: Grant
    Filed: June 30, 1997
    Date of Patent: October 17, 2000
    Assignee: Philips Electronics North America Corp.
    Inventors: Subhas Bothra, Jacob Haskell