Patents Represented by Attorney Martine & Penilla, LLP
  • Patent number: 6839647
    Abstract: An invention is provided for testing in a Java based environment. The method includes launching a test harness in a first JVM, and starting a virtual machine (VM) agent in a second JVM. The VM agent is placed in communication with the test harness. The VM agent then executes a test application such that both the test application and the VM agent execute in the second JVM. In this manner, the VM agent is restarted using the test harness if the second JVM fails.
    Type: Grant
    Filed: September 10, 2002
    Date of Patent: January 4, 2005
    Assignee: Sun Microsystems, Inc.
    Inventors: Alexei Volkov, Allan S. Jacobs
  • Patent number: 6835979
    Abstract: A nonvolatile memory cell which is highly scalable includes a cell formed in a triple well. A select transistor can have a source which also acts as the emitter of a lateral bipolar transistor. The lateral bipolar transistor operates as a charge injector. The charge injector provides electrons for substrate hot electron injection of electrons onto the floating gate for programming. The cell depletion/inversion region may be extended by forming a capacitor as an extension of the control gate over the substrate between the source and channel of said sense transistor.
    Type: Grant
    Filed: June 12, 2000
    Date of Patent: December 28, 2004
    Assignee: Altera Corporation
    Inventors: David K. Liu, Ting-wah Wong
  • Patent number: 6833624
    Abstract: The invention provides overlapping row decode in a multiport memory. Overlapping row decode includes predecode wires positioned on a first metallization layer and configured to address wordline drivers of a first port. A second plurality of predecode wires is located on a third metallization layer and configured to address wordline drivers of a second port. The overlapping row decode includes a plurality of wordline connections that are formed on a second metallization layer between the first metallization layer and the third metallization layer. The wordline connections include a first and second portion. The first portion communicates with the first plurality of predecode wires and the wordline drivers of the first port. The second portion communicates with the second plurality of predecode wires and the wordline drivers of the second port.
    Type: Grant
    Filed: February 10, 2003
    Date of Patent: December 21, 2004
    Assignee: Artisan Components, Inc.
    Inventor: Scott T. Becker
  • Patent number: 6833679
    Abstract: Apparatus and method are provided for using a multi-element field emission cathode in a color cathode ray tube. The field emission cathode may have from four to ten field emission arrays linearly arranged. The arrays are preferably formed from carbon-based material. An electron gun assembly focuses electron beams from each array on to a phosphor stripe or dot on the screen of the cathode ray tube. Deflection apparatus moves the beam from each field emission array according to clock signals. Clock signals also turn on or turn off voltage to contacts controlling electron current from the array. Values of voltage applied, determined by a video signal, determine the intensity of electron current from each array, which controls the intensity of the light emitted by each color stripe or dot of phosphor on the phosphor screen.
    Type: Grant
    Filed: July 28, 2003
    Date of Patent: December 21, 2004
    Assignee: Trepton Research Group, Inc.
    Inventors: Byron G. Zollars, John J. Lorr, Kent R. Kalar
  • Patent number: 6833028
    Abstract: In a method for depositing particles onto a substrate a flow of gas containing particles is provided along a flow path that bypasses a deposition chamber. The flow path may direct the flow of the gas containing the particles to a vacuum. To deposit particles onto a substrate in the deposition chamber, the flow path of the gas containing the particles is diverted into the deposition chamber so that particles are deposited onto the substrate. After a desired amount of particles have been deposited onto the substrate, the flow path of the flow of the gas containing the particles is changed to the flow path that bypasses the deposition chamber. A particle deposition system and a method for maintaining particle diameter during deposition of particles onto a substrate also are described.
    Type: Grant
    Filed: February 11, 2002
    Date of Patent: December 21, 2004
    Assignee: The Scatter Works Inc.
    Inventors: Craig A. Scheer, John C. Stover
  • Patent number: 6831697
    Abstract: The present invention provides a surveillance camera with rotary camera lens comprising a body having a pair of opposed and spaced pivot supports with a receiving space formed therebetween, a pivotable lens seat having two ends and a pivot portion at each of these two ends, and a pivot assembly connected between one of the pair of pivot supports of the body and the pivot portion of the pivotable lens seat so that the pivotable lens seat may be pivotably connected to the body within the receiving space and stopped at any desired pivoting position.
    Type: Grant
    Filed: September 13, 2000
    Date of Patent: December 14, 2004
    Assignee: Tranwo Technology Corp.
    Inventor: Mu Jung Chang
  • Patent number: 6832180
    Abstract: A method for minimizing noise in an integrated circuit is described, the method including choosing a net to be analyzed, determining that the total path length of conductive paths coupled to a driver within the net exceed a maximum acceptable length for that given driver according to the minimum acceptable noise levels for that given net, and inserting at least one buffer within the net at a position which is within the maximum acceptable length for conductive paths coupled to the driver.
    Type: Grant
    Filed: October 29, 1999
    Date of Patent: December 14, 2004
    Assignee: Sun Microsystems, Inc.
    Inventors: Massimo Sutera, Alan Smith
  • Patent number: 6832238
    Abstract: The present invention defines a transaction management contract between an application server and a resource adapter and its underlying resource manager that allows an application server to utilize local transactions on a resource manager and avoid the overhead of an external transaction manager. The transaction management contract incorporates two aspects that apply to different types of transactions. The first aspect provides an application level transaction contract between a transaction manager and a resource manager based on javax.transaction.xa.XAResource of the J2EE specification. The second aspect is local transaction management contract. These contracts enable application server to provide the infrastructure and runtime environment for transaction management. An application component relies on this transaction infrastructure to support its component level transaction model.
    Type: Grant
    Filed: May 24, 2000
    Date of Patent: December 14, 2004
    Assignee: Sun Microsystems, Inc.
    Inventors: Rahul Sharma, Vladimir Matena
  • Patent number: 6832294
    Abstract: An n-way interleaved set-associative external cache utilizes standard burst memory devices such as DDR (double data rate) memory devices. The interleaved set-associative cache organization scheme is designed to fully utilize burst efficiencies during snoop and invalidation operations. Cache lines are interleaved in such a way that a first burst transfer from the cache to the cache controller brings in a plurality of tags. The contents of the memory level device locations associated with each tag are stored in an alternating pattern in contiguous memory locations.
    Type: Grant
    Filed: April 22, 2002
    Date of Patent: December 14, 2004
    Assignee: Sun Microsystems, Inc.
    Inventors: Thomas M. Wicki, Koen R. C. Bennebroek
  • Patent number: 6828976
    Abstract: Embodiments of the present invention are directed to a method and apparatus for hardware acceleration of graphical fill in display systems. In one embodiment, a bit-mask is maintained. The bit-mask, termed the “filled color bitmap”, has one bit for each pixel of the display data. A register, termed the “filled color register”, capable of storing a single color value is maintained. When a write command is executed to fill a portion of the display memory with the same value that is stored in the filled color register, the bits in the filled color bitmap corresponding to the portion of display memory are set equal to 1. In executing other writes, the value is written to display memory and the bits in the filled color bitmap corresponding to the portion of display memory are set equal to 0. In one embodiment, the bitmap is located in a dynamic random access memory (DRAM).
    Type: Grant
    Filed: July 26, 2002
    Date of Patent: December 7, 2004
    Assignee: Sun Microsystems, Inc.
    Inventor: Lawrence L. Butcher
  • Patent number: 6827793
    Abstract: A method for cleaning a wafer with a drip nozzle being configured for use in a drip manifold that is oriented over a brush of a wafer cleaning system is provided. The drip nozzle has a first end and a second end with a passage defined there between where the passage includes a wall that extends longitudinally between the first end and the second end. An orifice is defined within the passage and located at the first end of the drip nozzle. The method includes inputting a fluid into the drip nozzle at an acute angle relative to a longitudinal extension of the wall and reflecting the fluid stream off an internal wall of the drip nozzle at least twice in a direction that is toward the second end. The method further includes outputting at least one substantially uniform drop from the second end of the passage.
    Type: Grant
    Filed: September 12, 2003
    Date of Patent: December 7, 2004
    Assignee: Lam Research Corporation
    Inventors: Don E. Anderson, Katrina A. Mikhaylich, Mike Ravkin, John M. de Larios
  • Patent number: 6827092
    Abstract: An apparatus for preparing a wafer is provided. The apparatus includes a wafer backside plate and a central shaft. The wafer backside plate has a top surface that includes a cylindrical edge lip, which defines a central aperture. The central shaft is designed to fit within the central aperture. The wafer backside plate is designed to automatically slide between an up position during rotational wager processing and a down position when the wafer is not in rotational wafer processing. A gap defined between the top surface of the wafer backside plate and the wafer is less when the wafer backside plate is in the up position than when the wafer backside plate is in the down position.
    Type: Grant
    Filed: December 22, 2000
    Date of Patent: December 7, 2004
    Assignee: Lam Research Corporation
    Inventors: Stephen M. Smith, Randolph E. Treur
  • Patent number: 6829680
    Abstract: A method for increasing the processing speed of database instructions using a page prefetch cache. More particularly, the method is executed on a microprocessor and reduces database cache misses and improves the processing speed. The method comprises enabling a page prefetch cache with a database application, issuing one or more page prefetch instructions, and determining whether the particular database page is in the page prefetch cache.
    Type: Grant
    Filed: January 5, 2000
    Date of Patent: December 7, 2004
    Assignee: Sun Microsystems, Inc.
    Inventors: Rabin Sugumar, Srikanth T Srinivasan, Partha P. Tirumalai
  • Patent number: 6825708
    Abstract: An apparatus and method for a sensing circuit for cancelling an offset voltage. Specifically, in one embodiment, a CMOS inverter amplifier amplifies an input signal present at an input node. A resistive feedback circuit is coupled to the CMOS inverter amplifier for cancelling an offset voltage that is associated with the CMOS inverter amplifier. This is accomplished by biasing the CMOS inverter amplifier to its threshold voltage. A bias circuit is coupled to the resistive feedback circuit for biasing MOSFET transistors in the resistive feedback circuit at a subthreshold conduction region. As such, the resistive feedback circuit presents a high impedance to the input node. A clamping circuit, coupled to the resistive feedback circuit, maintains operation of the transistors in the resistive feedback circuit in the subthreshold conduction region.
    Type: Grant
    Filed: October 29, 2003
    Date of Patent: November 30, 2004
    Assignee: Sun Microsystems, Inc.
    Inventors: Robert J. Drost, Ivan E. Sutherland
  • Patent number: 6825671
    Abstract: Apparatus and methods are disclosed for determining the critical length of a conductor. In one aspect, a system may include at least one device under test (DUT) including at least one test strip of a metal under test. The test strip may be formed from a series of segments of the metal under test. The system may be configured to detect electromigration in the DUT using Blech's law. The system may be further configured to detect a rising voltage drop across the metal strips under test, and furthermore to calculate the electrical resistance change of the metal strips under electromigration testing conditions. The obtained results may be applied to ULSI design stage to improve the EM rule violation examination.
    Type: Grant
    Filed: February 22, 2002
    Date of Patent: November 30, 2004
    Assignee: Sun Microsystems, Inc.
    Inventor: Wei Zhang
  • Patent number: 6826523
    Abstract: An application interface and method for developing multi-user applications executable over a distributed network is described. An object definition structure is provided for client-based definition of objects utilized by a multi-user application. The object definition includes a plurality of characteristics associated with the object and utilized by the application to effect interaction with other clients over the distributed network. A broadcast schedule is associated with one or more of the plurality of characteristics and controls the transmission of object data from the creating client to other clients in the distributed network. During execution of the multi-user application, characteristics of the object are automatically updated periodically or upon the change of a characteristic relative to a preset threshold value, in accordance with values provided in the broadcast schedule.
    Type: Grant
    Filed: November 1, 2000
    Date of Patent: November 30, 2004
    Assignee: Sony Computer Entertainment America Inc.
    Inventors: Charles H. Guy, Glen A. Van Datta, João A. Fernandes
  • Patent number: 6822236
    Abstract: A method optimizes gas correlation radiometer response to trace amounts of target gas in the free atmosphere in competition with interfering gas. Operations identify spectral regions of a first absorption spectrum of the target gas, and of a second absorption spectrum of the interfering gas. A set of similarity data is determined as a function of overlap regions within the spectral region, and a set of contrast data is determined as a function of non-overlap regions within the spectral region, including a plurality of data items within each of a plurality of bandwidths, and a data item corresponding to a center wavelength within each bandwidth. Graphs correspond to each bandwidth. From one graph a center wavelength of an infrared filter is selected, and from another graph there is selected a bandwidth of the infrared filter, to configure an infrared filter for use with the gas correlation radiometer.
    Type: Grant
    Filed: March 18, 2004
    Date of Patent: November 23, 2004
    Assignee: Ophir Corporation
    Inventors: Loren D. Nelson, Martin J. O'Brien
  • Patent number: 6821195
    Abstract: An invention is provided for a carrier head for use in a CMP process. The carrier head includes a metal plate that is capable of transferring a downforce to a wafer during a CMP operation. A plurality of vacuum holes is disposed within the metal plate, wherein each vacuum hole is positioned such that the vacuum hole is within five millimeters of an edge of the wafer during the CMP operation. In this manner, each vacuum hole can be positioned such that the vacuum hole is within an edge exclusion zone of the wafer during the CMP operation. In some embodiments, each vacuum hole is positioned such that the vacuum hole is within three millimeters of the edge of the wafer during the CMP operation, such as 2.7 millimeters from the edge of the wafer.
    Type: Grant
    Filed: June 28, 2002
    Date of Patent: November 23, 2004
    Assignee: Lam Research Corporation
    Inventors: Xuyen Pham, Ren Zhou, Raisa Khavinson
  • Patent number: 6822864
    Abstract: The invention provides a heat-dissipating assembly and a securing device used therein, which utilizes a way of securing by applying force in one direction to prevent the surface of a chip from being damaged. The securing device includes a frame body having a plurality of first fasteners fastened to a socket by the first fasteners; and a wrenching member pivotally coupled to the frame body, wherein after applying an external force on the wrenching member in one direction, the heat-dissipating device can be fixed tightly on the socket.
    Type: Grant
    Filed: December 4, 2002
    Date of Patent: November 23, 2004
    Assignee: Delta Electronics, Inc.
    Inventors: Wen-shi Huang, Kuo-cheng Lin, Fu-hau Tsai, Yu-hung Huang
  • Patent number: 6822325
    Abstract: Temperature sensitive devices may be shielded from temperature generating devices on the same integrated circuit by appropriately providing a trench that thermally isolates the heat generating devices from the temperature sensitive devices. In one embodiment, the trench may be formed by a back side etch completely through an integrated circuit wafer. The resulting trench may be filled with a thermally insulating material.
    Type: Grant
    Filed: August 1, 2002
    Date of Patent: November 23, 2004
    Assignee: Altera Corporation
    Inventor: Ting-Wah Wong