Abstract: A reconfigurable built-in self-test (“BIST”) engine for testing a reconfigurable memory is disclosed. The BIST engine executes a test on a memory for detecting faults. If the memory under test fails the test executed by the BIST engine, a decision is made depending on whether it is possible to reconfigure the memory under test. If memory reconfiguration is possible, the memory under test is reconfigured, such as by disabling the bad half of the memory under test. Once the memory under test is reconfigured, the BIST engine is also reconfigured in a manner appropriate for the type of BIST engine—centralized or distributed. In the case of a centralized BIST engine, a centralized BIST controller is modified to generate addresses corresponding only to the good half of the memory under test.

Abstract: A pick-up tool for the mounting of semiconductor chips onto a substrate has a suction device which consists of a plate made out of a dimensionally stable material one surface of which has structures made of hardened adhesive. The material for the plate is, for example, aluminum, a carbon fiber composite material or a dimensionally stable plastic. A suitable material for the structure is, for example, an adhesive which has Teflon® as the filing material.

Abstract: A symmetric multiprocessor system includes a first processor and a second processor for executing a multi-threaded process on packets, a first inbound interface and a first outbound interface associated with the first processor, a first task queue accessible for reading by the first processor, a second inbound interface and a second outbound interface associated with the second processor, and a second task queue accessible for reading by at least the first processor. The first inbound interface receives incoming packets and has a first input buffer maintaining a first input queue of the packets for processing by the first processor. The first outbound interface receives packets from the first processor and transmits outgoing packets. The first task queue receives packets output from at least the second processor and maintains another input queue of the packets for processing by the first processor and which are outgoing from the first outbound interface.

Abstract: A high reliability computer system includes a first and a second processing engine (PE), circuitry for switching control of the system from the first PE operating as a primary PE to the second PE upon detection of a failure of the first PE, at least one shared resource associated with both the first and second PEs, at least one dedicated resource associated with the first PE and at least one dedicated resource associated with the second PE, a database associated with and accessible by one of the first and second PEs and a configuration engine. The database contains initialization information for the one PE, including a first class of instructions affecting the shared resource and a second class of instructions affecting the dedicated resource of the one PE. The second class of instructions includes setting an enable password or a surrogate therefor for the one PE. The configuration engine is associated with the one PE and is operable in one of a first mode and a second mode.