Patents Represented by Attorney Matrix Semiconductor, Inc.
  • Patent number: 7049678
    Abstract: Hetero-structure semiconductor devices having first and second-type semiconductor junctions are disclosed. The hetero-structures are incorporated into pillar and rail-stack memory circuits improving the forward-to-reverse current ratios thereof.
    Type: Grant
    Filed: September 25, 2002
    Date of Patent: May 23, 2006
    Assignee: Matrix Semicoductor, Inc.
    Inventor: Thomas H. Lee
  • Patent number: 7026212
    Abstract: An improved method for fabricating a three dimensional monolithic memory with increased density. The method includes forming conductors preferably comprising tungsten, then filling and planarizing; above the conductors forming semiconductor elements preferably comprising two diode portions and an antifuse, then filling and planarizing; and continuing to form conductors and semiconductor elements in multiple stories of memories. The arrangement of processing steps and the choice of materials decreases aspect ratio of each memory cell, improving the reliability of gap fill and preventing etch undercut.
    Type: Grant
    Filed: May 26, 2004
    Date of Patent: April 11, 2006
    Assignee: Matrix Semiconductors, Inc.
    Inventors: S. Brad Herner, Maitreyee Mahajani
  • Patent number: 7012299
    Abstract: The traditional nitride-only charge storage layer of a SONOS device is replaced by a multifilm charge storage layer comprising more than one dielectric material. Examples of such a multifilm charge storage layer are alternating layers of silicon nitride and silicon dioxide, or alternating layers of silicon nitride and aluminum oxide. The use of more than one material introduces additional barriers to migration of charge carriers within the charge storage layer, and improves both endurance and retention of a SONOS-type memory cell comprising such a charge storage layer.
    Type: Grant
    Filed: September 23, 2003
    Date of Patent: March 14, 2006
    Assignee: Matrix Semiconductors, Inc.
    Inventors: Maitreyee Mahajani, Andrew J. Walker, En-Hsing Chen
  • Patent number: 7009275
    Abstract: An improved method for fabricating a three dimensional monolithic memory with increased density. The method includes forming conductors preferably comprising tungsten, then filling and planarizing; above the conductors forming semiconductor elements preferably comprising two diode portions and an antifuse, then filling and planarizing; and continuing to form conductors and semiconductor elements in multiple stories of memories. The arrangement of processing steps and the choice of materials decreases aspect ratio of each memory cell, improving the reliability of gap fill and preventing etch undercut.
    Type: Grant
    Filed: May 26, 2004
    Date of Patent: March 7, 2006
    Assignee: Matrix Semiconductor, Inc.
    Inventors: S. Brad Herner, Maitreyee Mahajani
  • Patent number: 6995422
    Abstract: An improved method for fabricating a three dimensional monolithic memory with increased density. The method includes forming conductors preferably comprising tungsten, then filling and planarizing; above the conductors forming semiconductor elements preferably comprising two diode portions and an antifuse, then filling and planarizing; and continuing to form conductors and semiconductor elements in multiple stories of memories. The arrangement of processing steps and the choice of materials decreases aspect ratio of each memory cell, improving the reliability of gap fill and preventing etch undercut.
    Type: Grant
    Filed: May 26, 2004
    Date of Patent: February 7, 2006
    Assignee: Matrix Semiconductor, Inc.
    Inventors: S. Brad Herner, Maitreyee Mahajani
  • Patent number: 6984561
    Abstract: An improved method for fabricating a three dimensional monolithic memory with increased density. The method includes forming conductors preferably comprising tungsten, then filling and planarizing; above the conductors forming semiconductor elements preferably comprising two diode portions and an antifuse, then filling and planarizing; and continuing to form conductors and semiconductor elements in multiple stories of memories. The arrangement of processing steps and the choice of materials decreases aspect ratio of each memory cell, improving the reliability of gap fill and preventing etch undercut.
    Type: Grant
    Filed: May 26, 2004
    Date of Patent: January 10, 2006
    Assignee: Matrix Semiconductor, Inc.
    Inventors: S. Brad Herner, Maitreyee Mahajani
  • Patent number: 6960794
    Abstract: A thin film transistor with a channel less than 100 angstroms thick, preferably less than 80 angstroms thick, preferably less than 60 angstroms thick. The very thin channel reduces variability of threshold voltage from one TFT to the next. This is particularly advantageous for TFT memory arrays. It is possible that an extremely thin channel restricts the size of grains, forcing many small grains to be formed.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: November 1, 2005
    Assignee: Matrix Semiconductor, Inc.
    Inventors: Andrew J. Walker, S. Brad Herner, Maitreyee Mahajani, En-Hsing Chen, Roy E. Scheuerlein, Sucheta Nallamothu, Mark Clark
  • Patent number: 6960495
    Abstract: A method for forming a contact in a three dimensional monolithic memory is disclosed. In a preferred embodiment, the method comprises depositing a conductive layer over and in contact with a plurality of antifuses, wherein said antifuses are part of a story of active devices formed above a substrate; patterning and etching said conductive layer and insulating dielectric to form a contact void; and filling the contact void, wherein the conductive layer does not comprise silicon.
    Type: Grant
    Filed: May 26, 2004
    Date of Patent: November 1, 2005
    Assignee: Matrix Semiconductor, Inc
    Inventors: Michael Vyvoda, S. Brad Herner
  • Patent number: 6951780
    Abstract: The present invention relates to use of selective oxidation to oxidize silicon in the presence of tungsten and/or tungsten nitride in memory cells and memory arrays. This technique is especially useful in monolithic three dimensional memory arrays. In one aspect of the invention, the silicon of a diode-antifuse memory cell is selectively oxidized to repair etch damage and reduce leakage, while exposed tungsten of adjacent conductors and tungsten nitride of a barrier layer are not oxidized. In some embodiments, selective oxidation may be useful for gap fill. In another aspect of the invention, TFT arrays made up of charge storage memory cells comprising a polysilicon/tungsten nitride/tungsten gate can be subjected to selective oxidation to passivate the gate polysilicon and reduce leakage.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: October 4, 2005
    Assignee: Matrix Semiconductor, Inc.
    Inventor: S. Brad Herner
  • Patent number: 6952030
    Abstract: A three dimensional monolithic memory comprising a memory cell allowing for increased density is disclosed. In the memory cell of the present invention, a bottom conductor preferably comprising tungsten is formed. Above the bottom conductor a semiconductor element preferably comprises two diode portions and an antifuse. Above the semiconductor element are additional conductors and semiconductor elements in multiple stones of memories. The arrangement of processing steps and the choice of materials decreases aspect ratio of each memory cell, improving the reliability of gap fill and preventing etch undercut.
    Type: Grant
    Filed: May 26, 2004
    Date of Patent: October 4, 2005
    Assignee: Matrix Semiconductor, Inc.
    Inventors: S. Brad Herner, Maitreyee Mahajani
  • Patent number: 6946719
    Abstract: The invention provides for a vertically oriented junction diode having a contact-antifuse unit in contact with one of its electrodes. The contact-antifuse unit is formed either above or below the junction diode, and comprises a silicide with a dielectric antifuse layer formed on and in contact with it. In preferred embodiments, the silicide is cobalt silicide, and the antifuse preferably silicon oxide, silicon nitride, or silicon oxynitride grown on the colbalt silicide. The junction diode and contact-antifuse unit can be used as a memory cell, which is advantageously used in a monolithic three dimensional memory array.
    Type: Grant
    Filed: December 3, 2003
    Date of Patent: September 20, 2005
    Assignee: Matrix Semiconductor, Inc
    Inventors: Christopher J. Petti, S. Brad Herner