Abstract: For one disclosed embodiment, an apparatus comprises a display and a circuit. The circuit has a first port to be coupled to communicate over data lines with a Universal Serial Bus (USB) port of a device external to the apparatus. The circuit is operable to detect resume signaling of a duration of less than one millisecond and to transition the first port from a first state corresponding to an idle state of the data lines to a second, enabled state in response to the resume signaling. For one disclosed embodiment, the circuit is operable to drive resume signaling for a duration of less than one millisecond to initiate transition of the first port from a first state corresponding to an idle state of the data lines to a second, enabled state. Other embodiments are also disclosed.

Abstract: For one disclosed embodiment, an apparatus comprises first circuitry to output encoded data from an addressable location based at least in part on an address corresponding to a first number, wherein the encoded data is based at least in part on data that corresponds to the first number and that is encoded for partial product reduction, and second circuitry to generate a product based at least in part on the encoded data and on data corresponding to a second number. Other embodiments are also disclosed.

Abstract: For one disclosed embodiment, switching voltage regulator circuitry may be controlled to supply a voltage to at least a portion of an integrated circuit. Information corresponding to a current load for a different power state of at least a portion of the integrated circuit may be received. The switching voltage regulator circuitry may be controlled to adjust the voltage to a different value based at least in part on the received information. For another disclosed embodiment, a voltage may be received for a power state of at least a portion of an integrated circuit having first logic to perform one or more functions and second logic integrated with the first logic. Information corresponding to a current load for a different power state of at least a portion of the integrated circuit may be sent from the second logic to voltage regulator control logic to adjust the voltage to a different value. Other embodiments are also disclosed.

Abstract: For one embodiment, an apparatus comprises memory circuitry including memory cells, error detection circuitry to detect error in data stored by memory cells of the memory circuitry, and supply voltage control circuitry to increase supply voltage for one or more memory cells of the memory circuitry based at least in part on detected error. Other embodiments have one or more other features.

Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A voltage regulator may be coupled to a processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero while an external voltage is continuously applied to a portion of the processor to save state variables of the processor during the zero voltage management power state.

Abstract: A method and apparatus is described for computing a duration of a reduced power consumption state. A time of exiting from the reduced power consumption state is read prior to an execution of an interrupt routine. The read time of exiting is then stored in a register and a calculation of a reduced power consumption state duration may be performed.

Abstract: For one disclosed embodiment, power from a backup battery may be received by first circuitry. One or more other batteries different than the backup battery may be tested with the first circuitry. Second circuitry may be allowed to supply power from at least one of the one or more other batteries to at least one electronic component at startup based at least in part on the test having a first result. Startup of the at least one electronic component may be prevented based at least in part on the test having a second result. Other embodiments are also disclosed.

Abstract: For one disclosed embodiment, an apparatus comprises a load circuit having one or more memory devices, one or more temperature sensors to sense one or more temperatures for the load circuit, and supply voltage control circuitry to control supply voltage to be applied to the load circuit. The supply voltage control circuitry may vary the supply voltage based at least in part on one or more sensed temperatures when the load circuit is in an inactive state and may help retain one or more signals by one or more memory devices of the load circuit as the supply voltage is varied. Other embodiments are also disclosed.

Abstract: For one disclosed embodiment, an apparatus may comprise a first die including a first plurality of memory cells for a memory array and a second die including a second plurality of memory cells for the memory array. The second die may include a shared line for the memory array to conduct digital signals for memory cells of both the first and second plurality of memory cells. Other embodiments are also disclosed.

Abstract: For one embodiment, an apparatus may include a memory cell to store a bit value, wherein the memory cell may lose the bit value in response to a memory access operation. The apparatus may also include first circuitry to detect whether the memory cell loses the bit value in response to the memory access operation and second circuitry to restore the bit value in the memory cell in response to detection that the memory cell loses the bit value. Other embodiments include other apparatuses, methods, and systems.

Abstract: Power consumption of an address bus interface is reduced by reducing drive duration of address signals on the address bus. The address bus interface may operate in normal or power saving mode. In power saving mode, address signals are driven for a quarter of a clock period instead of half a clock period and address strobe edges are moved so that they are aligned with valid address signals.

Abstract: A system including at least one electronic component and a battery check circuit. When a power consumption level of the at least one electronic component is increased, the battery check circuit determines whether to provide power from a battery to the at least one electronic component by comparing a power level of the battery to a first power level.

Abstract: A memory element which includes a family of fault-tolerant storage elements using complementary metal-oxide-semiconductor (CMOS) technology is provided. The memory element provides arbitrary levels of redundancy, allowing the tolerance of multiple single event upsets due to particle hits. The memory element may be used in memory arrays such as caches and register files, and clocked registers and latches found in data path and control structures.

Abstract: A method and apparatus for performing majority voting is presented. The method selects pairs of inputs, performs AND and NOR operations on each pair of inputs to determine that each pair of inputs is both high or both low, yielding a quantity of “both high” pairs and a quantity of “both low” pairs, and compares the quantity of “both high” pairs against the quantity of “both low” pairs to determine the majority. The apparatus includes AND gates configured to receive pairs of values and NOR gates configured to receive the same pairs of values, with a connections between all AND gates and connections between all NOR gates. A summation element sums all AND gate outputs and all NOR gate outputs to determine the majority.

Abstract: A method to handle data dependencies in a pipelined computer system is disclosed. The method includes allocating a plurality of registers, enabling execution of computer instructions concurrently by using the plurality of registers, and tracking and reducing data dependencies in the computer instructions by correlating a busy condition of a computer instruction to each register.

Abstract: A method for designing and testing on-die power supply, power distribution, and noise suppression techniques for integrated circuits such as microprocessors is described. A network of time varying loads is distributed along the power supply grid to facilitate testing of new power supplies and grids and noise suppression techniques before design of the chip is completed. Several programmable current sinks are described for presenting loads according to a preferred test-waveform current. Transient, including droop detection, and static testing is easily performed using the described methods and circuitry.

Abstract: A device includes a bus, a first transmitter connected to the bus and configured to transmit a first signal over the bus in a first frequency band, a second transmitter connected to the bus and configured to transmit a second signal over the bus in a second frequency band at the same time that the first transmitter is transmitting the first signal, a first receiver connected to the bus and configured to receive the first signal transmitted over the bus in the first frequency band, and a second receiver connected to the bus and configured to receive the second signal transmitted over the bus in the second frequency band. The first frequency band and the second frequency band occupy different portions of the frequency spectrum.

Abstract: Briefly, in accordance with one embodiment of the invention, a portable communication device includes two processors. A power management controller may be adapted to alter an operational characteristic of the processors. In an alternative embodiment, the power management controller may be further adapted to vary an operational characteristics of one processor while leaving the other processor substantially unchanged.

Abstract: A transition encoded dynamic bus includes an encoder circuit at the input to the bus and a decoder circuit at the output to the bus. The encoder circuit generates a signal indicative of a transition at the input to the bus rather than the actual value at the input. The decoder circuit decodes the transition encoded information to track the appropriate value to be output from the bus.

Abstract: Briefly, in accordance with an embodiment of the invention, a method to generate cache data is provided, wherein the method includes identifying access data transmitted from a storage device during execution of a predetermined software program and generating cache data using the identified access data.